Power Optimization and Testing of Sequential Machines

1. Topics • State assignment. • Power optimization of sequential machines. • Design validation. • Sequential testing.

2. State assignment • Encoding bits in symbolic state = state assignment. • State assignment affects: • combinational logic area; • combinational logic delay; • memory element area.

3. State assignment in n-space

4. State assignment and delay

5. Power optimization Memory elements stop glitch propagation:

6. Sequential testing • Much harder than combinational testing - can’t set memory element values directly. • Must apply sequences to put machine in proper state for test, be able to observe value of test.

7. Example

8. Testing the machine • To test NOR for stuck-at-1, must set both NOR inputs to 0. • Primary input i1 can be controlled directly. • To set lower NOR input, must set state to ps0 = ps1 = 0.

9. Example state machine State codes: s0 = 11 s1 = 10 s2 = 01 s3 = 00

10. Controlling an FSM • Don’t know initial state of machine. • Must find a sequence which drives machine to required state independent of initial state. • State sequence for test: * -> s0 -> s1 -> s3.

11. Time-frame expansion • A model for sequential test: unroll machine in time. • Time frame expansion illustrates how single-stuck-at fault in sequential machine appears to be multiple-SA fault.

12. Time-frame expansion example

14. Unreachable states • State assignment may cause some states to be unreachable. • As a result, it may not be possible to apply some required test values.

15. Unreachable state example

16. Example • State codes: • s0 = 00 • s1 = 01 • s2 = 10. • This creates a fourth state which is unreachable.

17. Implemented FSM

19. LSSD • LSSD = level-sensitive scan design. • Way to achieve full controllability, observability of registers. • Links all registers in a scan chain.

20. LSSD latch

21. Partial scan • Full scan is expensive - must roll out and roll in state many times during a set of tests. • Partial scan selects some registers for scanability. • Requires analysis to choose which registers are best for scan.