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Oliver Diessel, UNSW Grant Wigley and David Kearney, UniSA

Operating Systems Support for Dynamically Reconfigurable Architectures » Run-time Partitioning for Just-in-time Compilation «. Oliver Diessel, UNSW Grant Wigley and David Kearney, UniSA. Outline. Motivate OS for Multi-tasking RS Some design options Task scheduling Compilation goals Models

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Oliver Diessel, UNSW Grant Wigley and David Kearney, UniSA

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  1. Operating Systems Support for Dynamically Reconfigurable Architectures» Run-time Partitioning for Just-in-time Compilation « Oliver Diessel, UNSW Grant Wigley and David Kearney, UniSA

  2. Outline • Motivate OS for Multi-tasking RS • Some design options • Task scheduling • Compilation goals • Models • Task partitioning

  3. Motivation for Multi-tasking • Growing size of reconfigurable logic resource • Growing range and integration of applications • Orientation towards real-time tasks • How to manage/support large reconfigurable logic resource in a multitasked environment? • space- or time-shared? • fixed or variable partitioning?

  4. Pros “easy” to design for supports location independence & fault tolerance “easy” to manage Cons task performance can suffer internal fragmentation Fixed Partition Size

  5. Pros allocation flexibility allows optimal performance to be achieved better utilization possible Cons need to cope with dynamic resource availability — scheduling complexity external fragmentation Variable Partition Size

  6. Coping with Variably Sized Tasks • Wait for or preempt executing tasks • Move executing tasks to free up space • Adapt incoming task to space available at run time • requires fast partitioning, placement, and routing • requires on-line scheduling of • logic • routing resources • pins • memory

  7. Long-Term Goals 1. Develop accurate and efficient indicators that can tell us whether to accept or reject real-time reconfigurable computing tasks into common architectural models. 2. Develop algorithms and techniques that allow us to complete the physical design of tasks without contributing significantly to overheads.

  8. Task Netlisted combinational task graph (DAG) each vertex has associated area and latency each edge has associated width Dataset representing given number of cycles Off-line processing Machine Single context logic resource of given area and pin count Assume fixed clock period Given amount of fast local buffer memory Assume reconfiguration time proportional to sum of vertex areas, sum of edge weights, and number of pins in config Models

  9. Partitioning Goal • Determine partitioning of DAG and a configuration sequence (subject to correctness, area, latency, pin, and buffer size constraints) that identifies for each partition the number of cycles it should execute for in order to minimize the total execution time • Do so quickly

  10. First steps

  11. Previous work in area • Partitioning • Survey: Alpert & Kahng, Integration, Aug 95 • Single Context:GajjalaPurna & Bhatia, TOC, Jun 99; Kaul & Vemuri, RAW99 • Multiple Context: Trimberger, FPGA98; Liu & Wong, FPGA99; Chang & Marek-Sadowska, TOC, Jun 99 • Placement • Sankar & Rose, FPGA99 • Routing • Swartz, Betz & Rose, FPGA98

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