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Low-Power CMOS Design

Low-Power CMOS Design. For Advanced VLSI Design and VLSI Signal Processing Courses 12-04-2002 台大電機系 吳安宇 教授. Data Source. “Low-power Circuit Design Basics,” by Prof. Jan M. Rabaey, UC Berkerly, in tutorial of ISCAS, London, 1994.

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Low-Power CMOS Design

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  1. Low-Power CMOS Design For Advanced VLSI Design and VLSI Signal Processing Courses 12-04-2002 台大電機系 吳安宇 教授

  2. Data Source • “Low-power Circuit Design Basics,” by Prof. Jan M. Rabaey, UC Berkerly, in tutorial of ISCAS, London, 1994. • “Can we simultaneously achieve High Speed and Low Power in IC Design?” by Prof. Wentai Liu in 7th VLSI/CAD Symposium, 1996. • Chapter 17 of Textbook “VLSI Digital Signal Processing Systems: Design and Implementation," by K. K. Parhi, Wiley-Interscience Publication, 1999.

  3. Low Power Design – An Emerging Discipline • Historical figure of merit for VLSI design – performance (circuit speed) and chip area (circuit density/cost). But • Power dissipation is now an important metric in VLSI design. • No single major source for power savings across all design levels – Required a new way of THINKING!!! • Companies lack the basic power-conscious culture and designers need to be educated in this respect. • Overall Goal – To reduce power dissipations but maintaining adequate throughput rate.

  4. Motivation - Microprocessor

  5. Motivation - Microprocessor

  6. Competitive Reasons – Low Power • Battery Powered Systems – Extended Battery Life and reduce weight and size. • High-Performance Systems • Cost • Package (chip carrier, heat sink, card slots, plenum, …) • Power Systems (supplies, distribution, regulators, …) • Fans (noise, power, reliability, area, …) • Operating cost to customer – Energy Star issue. • Reliability • Failure rate increase by 4X for Tj @ 110C vs 70C • Mission critical operation at 100C • Size and Weight – Product footprint (office and deskspace)

  7. The Power Crisis : Portability Expected Battery Lifetime increase Over next 5 years: 30-40% PDA, Cellular Phone, Notebook Computer,etc.

  8. A Multimedia Terminal – The Infopad Present day battery technology (year 1990) – 20 lbs for 10hrs

  9. IC Design Space

  10. Low Power Design • Source of power disspation • P = P switching + P short-circuit + Pleakage + P static • Definitions: • Switching power P = CV2fα • Short circuit power P = IscV • Leakage power P = IleakageV • Static power P = IstaticV • α : switching activity factor • Low power design would look at the trade-offs of the above issues

  11. Dynamic Power Consumption • Not a function of transistor sizes! • Need to reduce CL, Vdd, and f ti reduce power • Reduce the probability, P0 -> 1 Energy/transition = CL * Vdd2 Power = Energy/transition * f = CL * Vdd2 * f

  12. Dynamic Power Consumption - Extended • Power = Energy/transition * transition rate = CL * Vdd2 * f0->1 = CL * Vdd2 * P0->1 * f = CEFF * Vdd2 * f • Power Dissipation is Data Dependent Function of Switching Activity • CEFF = Effective Capacitance = CL * P0->1

  13. Ultra Low Power System Design • Power minimization approaches: • Run at minimum allowable voltage • Minimize effective switching capacitance

  14. Process • Progress in SOI and bulk silicon • (a) 0.5V operation of ICs using SOI technology • (b) 0.9V operation of bulk silicon memory, logic, and processors • Increasing densities and clock frequencies have pushed the power up even with reduce power supply

  15. Choice of Logic Style

  16. Choice of Logic Style • Power-delay product improves as voltage decreases • The “best” logic style minimizes power-delay for a given delay constraint

  17. Power Consumption is Data Dependent • Example : Static 2 Input NOR Gate Assume : P(A=1) = ½ P(B=1) = ½ Then : P(Out=1) = ¼ P(0→1) = P(Out=0).P(Out=1) =3/4 * 1/4 = 3/16 CEFF = 3/16 * CL

  18. Transition Probability of 2-input NOR Gate as a function of input probabilities

  19. Switching Activity (α) : Example

  20. Glitching in Static CMOS

  21. At the Datapath Level… Irregular Reusable

  22. Balancing Operations

  23. Carry Ripple

  24. Data Representation

  25. Low Power Design Consideration (cont’) (Binary v.s. Gray Encoding)

  26. Resource Sharing Can Increase Activity (Separate Bus Structure)

  27. Resource Sharing Can Increase Activity (cont’d)

  28. Operating at the Lowest Possible Voltage! • Desire to operate at lowest possible speeds (using low supply voltages) • Use Architecture optimization to compensate for slower operation Approach : Trade-off AREA for lower POWER

  29. Reducing Vdd

  30. Lowering Vdd Increases Delay • Concept of Dynamic Voltage Scaling (DVS)

  31. Architecture Trade-offs : Reference Data Path

  32. Parallel Data Path

  33. Pipelined Data Path

  34. A Simple Data Path : Summary

  35. Computational Complexity of DCT Algorithms

  36. Power Down Techniques • Concept of Dynamic • Frequency Scaling (DFS)

  37. Energy-efficient Software Coding • Potential for power reduction via software modification is relatively unexploited. • Code size and algorithmic efficiency can significantly affect energy dissipation • Pipelining at software level- VLIW coding style • Examples -

  38. Power Hunger – Clock Network (Always Ticking) • H-Tree – design deficiencies based on Elmore delay model • PLL – every designer (digital or analog) should have the knowledge of PLL • Multiple frequencies in chips/systems – by PLL • Low main frequency, But • Jitter and Noise, Gain and Bandwidth, Pull-in and Lock Time, Stability … • Local time zone • Self-Timed • Asynchronous => Use Gated Clocks, Sleep Mode

  39. Power Analysis in the Design Flow

  40. Human Wearable Computing - Power • Wearable computing – embedding computer into clothing or creating a form that can be used like clothing • Current computing is limited by battery capacity, output current, and electrical outlet for recharging

  41. Conclusions • High-speed design is a requirement for many applications • Low-power design is also a requirement for IC designers. • A new way of THINKING to simultaneously achieve both!!! • Low power impacts in the cost, size, weight, performance, and reliability. • Variable Vdd and Vt is a trend (DVS and DFS) • CAD tools high-level power estimation and management • Don’t just work on VLSI, pay attention to Microelectromechanical Systems (MEMS) – lots of problems and potential is great.

  42. Applications • Portable Multimedia Terminal • Wireless C&C • System on Chip (From Dr. Yang of Windbond)

  43. Applications IWireless Computing/Communication

  44. Applications IIA Portable Multimedia Terminal

  45. Applications IIISystem Value of IC Product • Concept of lays

  46. Applications IVSystem on Chip • Entire system function • Logic + Memory • More than two types of devices • Allow more freedom in architecture • Const/Performance trade-off

  47. Applications VNew Opportunity for Taiwan IC Industry • PAST • Digital IC • µ P • IBM Compatible + MD-DOS • FUTURE • System On Chip • Reduce head-on competition on standard products • Technology will be available • Manufacturing Service available • Same starting point as other countries • Can have more R/D focus

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