Multitasking

1. STES Sinhgad Institute of Tech. & Science Dept. of Computer Engg. Pune-41 Multitasking Mr. Mahendra B. Salunke Asst. Prof. Dept. of Computer Engg., STES SITS, Narhe, Pune-41

2. Introduction • A task is a program which is running, or waiting to run while another program is running. • A task is invoked by an interrupt, exception, jump, or call. • The Pentium processor provides hardware support for multitasking. • There are two types of task-related descriptors which can occur in a descriptor table: • Task state segment descriptors and task gates. • When execution is passed to either kind of descriptor, a task switch occurs. Computer Engg. Dept. STES SITS Pune

3. A task switch is like a procedure call, but it saves more processor state information. • A task switch transfers execution to a completely new environment, the environment of a task. • This requires saving the contents of nearly all the processor registers, including the EFLAGS register and the segment registers. • Unlike procedures, tasks are not re-entrant. • A task switch does not push anything on the stack. The processor state information is saved in a data structure in memory, called a task state segment. Computer Engg. Dept. STES SITS Pune

4. Supporting Registers and Data Structures • Task state segment. • Task state segment descriptor. • Task register. • Task gate descriptor. Computer Engg. Dept. STES SITS Pune

5. TASK STATE SEGMENT • The processor state information needed to restore a task is saved in a type of segment, called a task state segment or TSS. Computer Engg. Dept. STES SITS Pune

6. Computer Engg. Dept. STES SITS Pune

7. Lower portion of TSS Computer Engg. Dept. STES SITS Pune

8. Middle Portion of TSS Computer Engg. Dept. STES SITS Pune

9. Upper portion of TSS Computer Engg. Dept. STES SITS Pune

10. Fields in TSS • Fields of a TSS are divided into two main categories: • Dynamic fields the processor updates with each task switch. • Static fields the processor reads, but does not change. These fields are set up when a task is created. Computer Engg. Dept. STES SITS Pune

11. Dynamic Fields • The general registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, and EDI). • The segment registers (ES, CS, SS, DS, FS, and GS). • The flags register (EFLAGS). • The instruction pointer (EIP). • The selector for the TSS of the previous task (updated only when a return is expected). Computer Engg. Dept. STES SITS Pune

12. Static fields • The selector for the task's LDT. • The CR3 register. • The logical address of the stacks for privilege levels 0, 1, and 2. • The T-bit (debug trap bit) which, when set, causes the processor to raise a debug exception when a task switch occurs. • The base address for the I/O permission bit map and interrupt redirection bitmap. Computer Engg. Dept. STES SITS Pune

13. TSS DESCRIPTOR • Like all other segments, TSS is also defined by a descriptor. TSS descriptors only may reside in the GDT. Computer Engg. Dept. STES SITS Pune

14. The Busy bit in the Type field indicates whether the task is busy. A busy task is currently running or waiting to run. • A Type field with a value of 9 indicates an inactive task; a value of 11 (decimal) indicates a busy task. • Tasks are not recursive. The processor uses the Busy bit to detect an attempt to call a task whose execution has been interrupted. • The Base, Limit, and DPL fields and the Granularity bit and Present bit have functions similar to their use in data-segment descriptors. • The Limit field must have a value equal to or greater than 67H, one byte less than the minimum size of a task state. • An attempt to switch to a task whose TSS descriptor has a limit less than 67H generates an exception. • A larger limit is required if an I/O permission map is used. A larger limit also may be required for the operating system, if the system stores additional data in the TSS. Computer Engg. Dept. STES SITS Pune

15. TASK REGISTER • The task register (TR) is used to find the current TSS. • The task register has both a visible part (i.e., a part which can be read and changed by software) and an invisible part (i.e., a part maintained by the processor and inaccessible to software). • The selector in the visible portion indexes to a TSS descriptor in the GDT. • The processor uses the invisible portion of the TR register to retain the base and limit values from the TSS descriptor. • Keeping these values in a register makes execution of the task more efficient, because the processor does not need to fetch these values from memory to reference the TSS of the current task. Computer Engg. Dept. STES SITS Pune

16. The path by which processor accesses TSS Computer Engg. Dept. STES SITS Pune

17. LTR and STR instructions • LTR (Load task register) loads the visible portion of the task register with the operand, which must index to a TSS descriptor in the GDT. • The LTR instruction also loads the invisible portion with information from the TSS descriptor. The LTR instruction is a privileged instruction; it may be executed only when the CPL is 0. • STR (Store task register) stores the visible portion of the task register in a general register or memory. Computer Engg. Dept. STES SITS Pune

18. TASK GATE DESCRIPTOR • A task gate descriptor provides an indirect, protected reference to a task. Computer Engg. Dept. STES SITS Pune

19. The DPL of a task gate controls access to the descriptor for a task switch. • A procedure may not select a task gate descriptor unless the selector's RPL and the CPL of the procedure are numerically less than or equal to the DPL of the descriptor. • A procedure with access to a task gate can cause a task switch, as can a procedure with access to a TSS descriptor. Computer Engg. Dept. STES SITS Pune

20. Both task gates and TSS descriptors are provided to satisfy three needs: • The need for a task to have only one Busy bit. Each task should have only one such descriptor. There may, however, be several task gates which select a single TSS descriptor. • The need to provide selective access to tasks. Task gates fill this need, because they can reside in an LDT and can have a DPL which is different from the TSS descriptor's DPL. • The need for an interrupt or exception to cause a task switch. Task gates also may reside in the IDT, which allows interrupts and exceptions to cause task switching. Computer Engg. Dept. STES SITS Pune

21. Task Gates reference the task Computer Engg. Dept. STES SITS Pune

22. TASK SWITCHING • The processor transfers execution to another task in any of four cases: 1. The current task executes a JMP or CALL to a TSS descriptor. 2. The current task executes a JMP or CALL to a task gate. 3. An interrupt or exception indexes to a task gate in the IDT. 4. The current task executes an IRET when the NT flag is set. Computer Engg. Dept. STES SITS Pune

23. A task switch steps • Check that the current task is allowed to switch to the new task. • Check that the TSS descriptor of the new task is marked present and has a valid limit • Save the state of the current task. • Load the TR register with the selector to the new task's TSS descriptor, set the new task's Busy bit, and set the TS bit in the CR0 register. • Load the new task's state from its TSS and continue execution. Computer Engg. Dept. STES SITS Pune

24. TASK LINKING • The Link field of the TSS and the NT flag are used to return execution to the previous task. • The NT flag indicates whether the currently executing task is nested within the execution of another task, and the Link field of the current task's TSS holds the TSS selector for the higher-level task, if there is one Computer Engg. Dept. STES SITS Pune

25. Nested Task Computer Engg. Dept. STES SITS Pune

26. E-mail: msalunke@gmail.com URL: www.microsig.webs.com Happy Learning... Computer Engg. Dept. STES SITS Pune