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Magic Bus Tests

Magic Bus Tests. Tested New Mbus with Pecl Tested TTL arbitration – single board TTL Arbitration – Tested with 2 Tracklist boards TTL Arbitration – Multiple Interface boards tested TTL arbitration seems to work very well Problems with Alpha – data sent to wrong address, sync errors

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Magic Bus Tests

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  1. Magic Bus Tests • Tested New Mbus with Pecl • Tested TTL arbitration – single board • TTL Arbitration – Tested with 2 Tracklist boards • TTL Arbitration – Multiple Interface boards tested • TTL arbitration seems to work very well • Problems with Alpha – data sent to wrong address, sync errors • Problems improved to 1 error in 30M L1A with different firmware • Needs additional work to fully understand the problem • Problems with Svtlist – holds boss and doesn’t send data • Test of Reces with new MagicBus • Problems in standalone test – data in Reces gets cleared (spare boards or bus?) • New Alpha firmware needed to readout Reces during data loading • D0 found problem in their tests and are improving firmware • Test of All interface boards (plus Reces) – no delay, no beam, 100M L1A, 0 Errors • Test of New Magic Bus in top crate with Pecl – run with beam for 1 week • Test of All boards with TTL arbitration – with beam. No errors => Default Running • Put in small delays (<1us) between boards.

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