On-the-fly Synthesis of Multi-Clock SVA

1. On-the-fly Synthesis of Multi-Clock SVA Jiang Long Andrew Seawright Paparao Kavalipati IWLS’ 2008

2. Outline • Introduction • Background and scope • Related works • Synthesizing multi-clock SVA • Single clock assertion compilation • Compile through rewriting • On-the-fly synthesis algorithm • Proof of correctness • Experimental results and conclusions

3. Formal Model for Multi-Clock Designs SVA Assertions RTL Design Clock Specification

4. Multi-Clock Modeling mclk

5. Objective • Synthesize SVA into Checker logic • Generic checker logic • Utilize existing FV framework/technique/optimization • Utilize existing multi-clock network • Optimize checker logic size • Number of sequentials and gates • Validation • Proof of correctness

6. SVA Abstract Grammar – Unclocked Sequence Sequences define language of words • Booleans b • Concatenation R1 ##1 R2 • Or R1 or R2 • Repetition R1 [*0:$] • Fusion R1 ##0 R2 • Intersect R1 intersect R2 • Local Variable b, v=e

7. SVA Abstract Grammar – Clocked Sequence • Grammar for clocked sequence S S ::= @(clk) R | ( S ##1 S) • Single clock @clk R • Multi-clock @clk1 R1 ##1 @clk2 R2

8. SVA Abstract Grammar - Property Properties evaluate true/false over words • Regular expression R • Implication R |-> P R |=> P • Or P1 or P2 • And P1 and P1 • Not not P

9. SVA Abstract Grammar - Property Properties evaluate true/false over finite words • Implication R |-> P R |=> P

10. SVA Multi-Clock Assertions

11. SVA Multi-Clock Assertions

12. SVA Multi-Clock Assertions

13. SVA Multi-Clock Assertions

14. SVA Multi-Clock Assertions

15. Related Work • Synthesis of regular expression + “actions” • Seawright / Brewer - synthesis of controllers • Synthesis of SVA • Pellauer / Lis / Baltus / Nikhil - using Blue Spec • Checkers in Formal Verification • Beer / Ben-David / Landver: on-fly-model checking of RCTL • Synthesis of SVA Local Variables • Long/Seawright • Multi-Clock assertion synthesis for verification • Ganai, et al. • Annotating OVL 2.0 with SVA • Long, Seawright, et al.

16. Contribution • Synthesize SVA into Checker logic • Adapt single-clock SVA compilation procedure • Generic checker logic • Utilize existing FV framework/technique/optimization • Utilize existing multi-clock network • Optimized checker logic size • Validation • Proof of correctness based on SVA semantics

17. Outline • Introduction • Background and scope • Related works • Synthesizing Multi-clock SVA • Single clock assertion compilation • Compile through semantic rewriting • Penalty: Double the checker logic size • On-the-fly synthesis algorithm • No penalty • Proof of correctness • Experimental results and conclusions

18. |=> Prop term ##1 R term [*2:M] Bool gnt term req0 req1 SVA compilation Property p_m1; @(posedge clk0) req0 ##1 req1[*2:M] |=> gnt; endproperty

19. |=> term ##1 term [*2:M] gnt term req0 req1 Recursive Construction

20. |=> term ##1 term [*2:M] gnt term req0 req1 Recursive Construction

21. ##1 R1 R2 AP start start AP start AP R1 R2 clk R1 ##1 R2

22. R1 ##0 R2 AP start start AP start AP R1 R2

23. R1 ##0 R2 AP start start AP start AP R1 R2 R is equivalent to (R ##0 1) (1 ##0 R)

24. Outline • Introduction • Background and scope • Related works • Synthesizing Multi-clock SVA • Single clock assertion compilation • Compile through semantic rewriting • Penalty: Double the checker logic size • On-the-fly synthesis algorithm • No penalty • Proof of correctness • Experimental results and conclusions

25. SVA Semantic Rewriting Rules

26. Rewriting: An Example

27. |=> |=> ##1 ##1 term ##1 [*2:3] ##1 [*0:$] term [*2:3] ##1 [*0:$] term term gnt term term [*0:$] term clk2&&gnt !clk2 term !clk0 clk0&&req0 term req0 clk1&&req1 req1 !clk1 Synthesize Through Rewriting

28. |=> |=> ##1 ##1 term ##1 [*2:3] ##1 [*0:$] term [*2:3] ##1 [*0:$] term term gnt term term [*0:$] term clk2&&gnt !clk2 term !clk0 clk0&&req0 term req0 clk1&&req1 req1 !clk1 Synthesiz3 Through Rewriting 1. Checker logic: Correct by Construction

29. |=> |=> ##1 ##1 term ##1 [*2:3] ##1 [*0:$] term [*2:3] ##1 [*0:$] term term gnt term term [*0:$] term clk2&&gnt !clk2 term !clk0 clk0&&req0 term req0 clk1&&req1 req1 !clk1 Synthesis Through Rewriting 1. Checker logic: Correct by Construction 2. Rewriting rule (2.1): size of the tree doubled

30. On-the-fly Synthesis • Motivation • Avoid the penalty from the rewriting • Model clock directly • Compilation procedure • Annotate syntax tree with clock information • Adapt to existing recursive compilation • Model clocked constructs directly • Proof of correctness through construction

31. |=> Prop term ##1 R term [*2:M] Bool gnt term req0 req1 Annotated Abstract Syntax Tree clk2 clk3 clk3 clk3 clk2 clk1 clk1 clk1 clk2 clk2 clk2 clk2

32. |=> Prop term ##1 R term [*2:M] Bool gnt term req0 req1 Annotated Abstract Syntax Tree clk2 clk3 clk3 clk3 clk2 clk1 clk1 clk1 clk2 clk2 clk2 clk2

33. |=> Prop term ##1 R term [*2:M] Bool gnt term req0 req1 Annotated Abstract Syntax Tree clk2 clk3 clk3 clk3 clk2 clk1 clk1 clk1 clk2 clk2 clk2 clk2

34. On-the-fly Model • Annotated node with a single clock • @clk (b) • @clk (R1 ##1 R2) • Annotated node with two different clocks • @clk1 R1 ##1 @clk2 R2

35. Basic Block 1: @clk(b)

36. Basic Block 2: @clk(R1 ##1 R2)

37. Basic Block 2: @clk(R1 ##1 R2)

38. Building Block 3: @clk1 R1 ##1 @clk2 R2

39. Building Block 3: @clk1 R1 ##1 @clk2 R2

40. Building Block 3: @clk1 R1 ##1 @clk2 R2 s0 <= ( R1.Ap && @clk1 ) || ( s0 && !@clk2 )

41. NFA View: @clk1 R1 ##1 @clk2 R2

42. Outline • Introduction • Background and scope • Related works • Synthesizing Multi-clock SVA • Single clock assertion compilation • Compile through semantic rewriting • Penalty: Double the checker logic size • On-the-fly synthesis algorithm • No penalty • Proof of correctness • Experimental results and conclusions

43. SVA Rewriting Rules

44. Proof of Correctness • Lemmas • R equals. R ##0 1 • R equals. 1 ##0 R

45. Proof of Correctness • Lemmas • R equals. R ##0 1 • R equals. 1 ##0 R • @clk R equals. @clk ( R ##0 1 ) • @clk R equals. @clk ( 1 ##0 R)

46. Proof of Correctness • Lemmas • R equals. R ##0 1 • R equals. 1 ##0 R • @clk R equals. @clk ( R ##0 1 ) • @clk R equals. @clk ( 1 ##0 R) • @clk R equals. @clk 1 ##0 @clk R • @clk R equals. @clk R ##0 @clk 1

47. Proof of Correctness • Lemmas • R equals. R ##0 1 • R equals. 1 ##0 R • @clk R equals. @clk ( R ##0 1 ) • @clk R equals. @clk ( 1 ##0 R) • @clk R equals. @clk 1 ##0 @clk R • @clk R equals. @clk R ##0 @clk 1 • @clk1 R1 ##1 @clk2 R2

48. Proof of Correctness • Lemmas • R equals. R ##0 1 • R equals. 1 ##0 R • @clk R equals. @clk ( R ##0 1 ) • @clk R equals. @clk ( 1 ##0 R) • @clk R equals. @clk 1 ##0 @clk R • @clk R equals. @clk R ##0 @clk 1 • @clk1 R1 ##1 @clk2 R2 • @clk1 (R1 ##0 1) ##1 @clk2 ( 1 ##0 R2 )

49. Proof of Correctness • Lemmas • R equals. R ##0 1 • R equals. 1 ##0 R • @clk R equals. @clk ( R ##0 1 ) • @clk R equals. @clk ( 1 ##0 R) • @clk R equals. @clk 1 ##0 @clk R • @clk R equals. @clk R ##0 @clk 1 • @clk1 R1 ##1 @clk2 R2 • @clk1 (R1 ##0 1) ##1 @clk2 ( 1 ##0 R2 ) • @clk1 R1 ##0 @clk11 ##1 @clk21 ##0 @clk2 R2

50. Proof • @clk1 R1 ##0 @clk11 ##1 @clk21 ##0 @clk2 R2