The Past and Future of WRTLT

1. The Past and Future of WRTLT Yinghua Min* and Hideo Fujiwara** *Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China **Faculty of Informatics, Osaka Gakuin University, Osaka, Japan 

2. Outline • Motivation for this invited talk • Outline • Historical retrospect • Re-considering RTL and high level testing • Challenges in WRTLT • Summary

3. Historical retrospect • The first IEEE Workshop on RTL ATPG & DFT, Oct. 2000, Hunan University, Changsha, China. • in a room with a Statue of Confucius in Yuelu Academy • a one thousand year university • But discussed modern IT technology in English

4. Yuelu Academy（岳麓书院）

5. WRTLT2000

6. The title changed • In 2002, WRTLT changed its title to Workshop on RTL and High Level Testing • RTL testing and high level testing have been more important than before • the IC complexity and technology has been largely advanced. • Most of the workshops have been in conjunction with ATS

7. What happens in recently years • Nanoscale IC industry requires more material and fabrication technologies. • Not logic, but physics and EE • Computer scientists may feel they could not help much in these areas. • The submitted papers for WRTLT are then not as many as expected, and many of those submissions are not related to RTL or high level testing. • However, WRTLT12 program is fruitful. • Activating the workshop

8. Re-considering RTL and high level testing • Categorizing test methodology • Fault-oriented • Function-oriented • fault-independent testing • realization-independent testing • In 1993, an ITC panel titled “Fault Coverage Numbers: What Do They Mean?” attracted about 400 people to discuss the use of fault models. • Fault coverage is based on fault models. • for ATPG and test metrics.

9. Comments on fault models • With the advance of IC density, complexity and technology, many defects cannot be reflected by stuck-at faults (SAF). • On the other hand, it is interesting to note that industry experience shows that some 100% SAF fault coverage leads ICs under test to be overtested. • Delay faults • path delay fault model ---- not practical • transition delay fault model ---- easy ATPG • even if 100% transition delay fault coverage does not mean free of delay faults • N-detection

10. Other faults • Bridging faults • It is unnecessary to consider any two line bridging. • Crosstalk effects • Based on layout information • Very complicated physical phenomenon • Power transfinite • A system level problem

11. Breaking through SAF model • A superscalar processor with superpipeline and reorder buffer cannot be tested as a combinational circuit, and even as a sequential circuit, whose sequential depth may reach to 1000 or even more. • it is more difficult for multi-core processors. • Timing, • Power, • Signal integrity and etc. • Functional testing, and system testing

12. Functional testing • Functionally verify operations at the design frequency. • In SOCs, some IP core detailed implementation may not be available. • Using a large test sequence or a test program • When the functional testing is sufficient to stop? • similar to a problem of software testing. • To test or verify a SystemC design, it is very difficult to count how many faults or bugs having to be covered.

13. System-Level Testing (SLT) • What is the goal of testing? • to minimize test escape • to eliminate any unnecessary test for cost reduction • SLT is to maintain low IC DPPM (defect parts per million) level.

14. Industrial test flow

15. SLT advantages • SLT failures are true failures and do not add to yield loss. • SLT is a DPPM reduction technique • Testing ICs with a system • Different performance requirements • Testing IC power states • Easy to identify faults in rejected ICs

16. SLT application • Nvidia reported how SLT can potentially save test cost by reducing fault yield loss, as correlation data suggests there is less overkill with SLT. • Replacing Final Test on ATE with SLT may be a better option. • Although very high coverage structural testing is applied at wafer sort and final test, still many faulty chips escape from testing, and later caught at SLT. • Reduce DPPM but require much longer test durations. • When a customer rejects a product, a true test escape should be identified, and avoided for the coming products.

17. Adaptive test • to stable production process • A higher overview at IC production • high-level database abstractions • encapsulate data from different stages of fabrication • Learn from the data

18. Advantages of successful adaptive testing • test time reduction, • test quality improvement, • improved data analysis ability • acceleration of yield learning • real-time statistics and information

19. Challenges for scan design • Yinghua Min, “Is the full scan design unshakeable?” WRTLT2009, Hong Kong, Nov. 2009 • The i.MX21 applications processor from Freescale includes an ARM926EJ-S core and a host of peripherals. The i.MX21 does not have boundary-scan capability. But, some build-in functional testing facilities are available.

20. ‘‘embedded’’ test instruments • Some of the ATE functions to be embedded in circuits including • built-in memory, logic, and I/O test engines; • temperature and voltage monitors; • debug instruments such as logic analyzers, scopes, and trace buffers. • P1687，P1800 standards ---- extension to 1149.1 • the need to ensure that the test logic and functional logic are set to the correct (safe) state before, during, and after the execution of the boundary-scan test.

21. Functional verification • Three concepts of SOC functional verification: assertions, coverage, and constraints. • Functional verification includes a language, analysis tools and methodology to support the concepts of assertion-based verification. • System Verilog assertions

22. What is an assertion? • An assertion, sometimes called a checker or monitor, is a precise description of what behavior is expected when a given input is presented to the design. • Any engineer who has ever written a line of C to print out an error message about a detected internal inconsistency has written an assertion. • Assertions that specify input or output protocols reflect not only just a single block, but rather the interaction between the block and its neighbors.

23. Assertion-based verification • Output assertions check that the results from the block agree with what is expected by the other blocks receiving the output signals. • Input assertions represent the range of inputs for which the block is designed. They screen out illegal inputs from other blocks. • Input assertions are treated as constraints.

24. SystemVerilog assertions • SystemVerilog assertionsare integrated in the hardware design language, Verilog. • It is in its standardization stage • two kinds of assertions: concurrent and immediate • Immediate: a single time step • Concurrent: multiple time steps with linear semantics • SVA has a layered structure: • Booleans, regular expressions (sequences), properties, and statements. • Coverage problem: syntax and simulation semantics

25. Challenges in WRTLT • We have had 12 workshops. • workshop is not a good place for paper publication, but a good opportunity for discussions among our test community. • A successful example is the IEEE semiconductor wafer test workshop (SWTW) in South California. It celebrates its 23rd year now. • It is not a sales show, nor an academic or theoretical conference. • Why success? • Common interests in searching for new research directions, new industrial experiences, and new ideas. • Manufacturers and vendors interesting in discussions.

26. Functional testing • Fail to establish a unified fault model • To check functions to be implemented • How many functions we should check? • Coverage metrics • to predict testing quality by tracing the test process instead • The same problem as software testing • Detecting more faults is better. • Software testing means • testing software, • testing hardware by using some specific software. • especially suitable for testing complex superscalar processors, as long as high level descriptions are available.

27. System testing • It tests hardware and software as a whole. • such as SOC testing • avoids unnecessary cost and overtested, • helps locating faults for rejected parts. • Including model checking, type checking • Delay testing, verification testing and secure testing • All high level testing techniques might be major themes of coming WRTLTs.

28. Summary • In order to attract more manufacturers and vendors involved in the workshop, we suggest select a specific theme for each WRTLT. • invite some industry people to give an opening presentation of the theme • Call for session proposals • panel session proposals • special session proposals. • The proposer is invited, and all panelists and special session contributors are collected by the proposer, and named invited speakers.

29. Hope coming WRTLTs successful ! Thank you for your attention!