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Independent internet Embedded system - MidTerm. Preformed by: Genady okrain Instructor: Tsachi Martsiano Duration : Two semesters - 2013. System Overview. Part A Goals. Transfer big files from the PC to the FPGA and back . Ethernet Interface. DDR Interface. Test data speeds.
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Independent internet Embedded system - MidTerm Preformed by: Genadyokrain Instructor: TsachiMartsiano Duration: Two semesters - 2013
Part A Goals • Transfer big files from the PC to the FPGA and back. • Ethernet Interface. • DDR Interface. • Test data speeds. • UDP Packets Analyzers: • Ostinato Packet/Traffic Generator and Analyzer. • Wiresharknetwork protocol analyzer.
MPMC • Double Data Rate (DDR/DDR2/DDR3/LPDDR) and Single Data Rate (SDR) SDRAM memory support. • Parameterizable: • number of ports (1 to 8) • number of data bits to memory (4, 8, 16, 32, 64) • configuration of data path FIFOs • Customize-able Interfaces: XCL, LocalLink (using SDMA), PLB v4.6 with Xilinx simplifications, NPI, MCB, MIB/PPC440MC, and VFBC
NPI PIM Features • Allows you to extend the capabilities of MPMC to meet your own design needs. • Offers a simple interface to memory that can easily be adapted to nearly any protocol. • Provides address, data, and control signals to enable read and write requests for memory. • Allows simultaneous push and pull of data from the port FIFOs. • MPMC supports the following transfer sizes: byte, half-word, word, double-word, 4-word cacheline, 8-word cacheline, 16-word bursts, 32-word bursts, and 64-word bursts.
Embedded Tri-Mode Ethernet MAC • Fully integrated 10/100/1000 Mb/s Ethernet MAC • Designed to the IEEE Std 802.3-2002 specification • Configurable full-duplex operation in 10/100/1000 Mb/s • Media Independent Interface (MII), Gigabit Media Independent Interface (GMII), and Reduced Gigabit Media Independent Interface (RGMII)
Clocks & Throughput • FPGA: • 125 Mhz • Microblaze: • 125 Mhz • DDR2@200 MHz 64 bits: • 1.6 Gbyte/sec • Ethernet: • 1 Gbit/sec