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CHAPTER 14

CHAPTER 14. Electrical Properties Of Materials. 14-1. Electric Conduction – Classical Model. Metallic bonds make free movement of valence electrons possible. Outer valence electrons are completely free to move between positive ion cores.

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CHAPTER 14

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  1. CHAPTER 14 Electrical Properties Of Materials 14-1

  2. Electric Conduction – Classical Model • Metallic bonds make free movement of valence electrons possible. • Outer valence electrons are completely free to move between positive ion cores. • Positive ion cores vibrate with greater amplitude with increasing temperature. • The motion of electrons are random and restricted in absence of electric field. • In presence of electric field, electrons attain directed drift velocity. 14-2

  3. Ohm’s Law • Ohm’s law states that electric current flow I is directly proportional to the applied voltage V and inversely proportional to resistance of the wire. i = V/Rwhere i = electric current (A) V = potential difference (V) R = resistance of wire (Ω) • Electric resistivity ρ = RA/l where l = length of the conductor and A = Cross-sectional area of the conductor. • Electric Conductivity σ = 1/ ρ • Microscopic Ohm's law J = E/ ρ J= Current density A/m2 E = electric field V/m Figure 13.3 14-3

  4. Drift Velocity of Electrons • Electrons accelerate when electric field E is applied and collide with ion cores . • After collision, they accelerate again. • Electron velocity varies in a saw tooth manner. • Drift velocityVd = μE where μ = electron mobility m2/(V.s) • Direction of current flow is apposite to that of electron flow. Figure 13.4 14-4

  5. Electrical Resistivity • Electrical resistivity ρtotal = ρT + ρr • ρT = Thermal component : Elastic waves (phonons) generated due to vibration of electron core scatter electrons. • Resistivity increases with temperature. • Alloying increases resistivity. • ρr= Residual component : Due to structural imperfections like dislocations. • ρT = ρ0C(1+αTT) ρ0C = Resistivity at 00C αT = Coefficient of resistivity. T = Temperature of the metal Figure 13.7 14-5

  6. Energy Bond Model of Electric Conduction • Valence electrons are delocalized, interact and interpenetrate each other. • Their sharp energy levels are broadened into energy bands. • Example:- Sodium has 1 valence electron (3S1). If there are N sodium atoms, there are N distinct 3S1 energy levels in 3S band. • Sodium is a good conductor since it has half filled outer orbital Figure 13.11 14-6

  7. Energy Band Model for Insulators • In insulators, electrons are lightly bound. • Large energy gap Eg Separates lower filled valence band and upper empty conduction band. • To be available for conduction, the electron should jump the energy gap. Figure 13.14 14-7

  8. Conduction in Intrinsic Semiconductors • Semiconductors: Conductors between good conductors and insulators. • Intrinsic Semiconductors: Pure semiconductors and conductivity depends on inherent properties. • Example: Silicon and Germanium – each atom contributes 4 valence electrons for covalent bond. • Valence electrons are excited away from their bonding position when they are excited. • Moved electron leaves a hole behind. Figure 13.16 14-8

  9. Electrical Charge Transport in Pure Silicon • Both electrons and holes are charge carriers. • Hole is attracted to negative terminal, electron to positive terminal. • Valence electron ‘A’ is missing – Hole • Valence electron ‘B’ moves to that spot due to the electric field leaving behind a hole. • Movement of electrons is apposite to electric field. Figure 13.19 Figure 13.18 14-9

  10. Quantitative Relationship of Electrical Conduction • J = nqVn* + PqVp* • Dividing by electric field E = J/σ • Vn/E and Vp/E are electron and hole mobilities μn, μp σ = nq μn + Pq μp n = p = ni Therefore σ = niq(μn+ μp) n = number of conduction electrons per unit volume. P = number of conduction holes per unit volume. q = absolute value of electron or hole charge = 1.6 x 10-19C Vn, Vp = drift velocities of electrons and holes. 14-10

  11. Effect of Temperature on Intrinsic Semiconductors • The conduction band is completely empty at 00K. • At higher temperatures, valence electrons are excited to conduction bands. • Conductivities increase with increasing temperature. ni= Concentrations of electrons having energy to enter conduction band. E= energy gap. Eav = average energy across gap. K = boatman's constant. T = temperature, K. σ0 = constant depending on the mobility. Since Since Or, 14-11

  12. Extrinsic Semiconductors • Extrinsic semiconductors have impurity atoms (100-1000 ppm) that have different valance characteristics. • n – type extrinsic semiconductors: Impurities donate electrons for conduction. • Example:- Group V A atoms ( P, As, Sb) added to silicon or Ge. Figure 13.22 Figure 13.21 14-12

  13. P-Type Extrinsic Semiconductors • Group III A atoms when added to silicon, a hole is created since one of the bonding electrons is missing. • When electric field is applied, electrons from the neighboring bond move to the hole. • Boron atom gets ionized and hole moves towards negative terminal. • B, Al, provide acceptor level energy and are hence called acceptor atoms. • Doping: Impurity atoms (dopants) are deposited into silicon by diffusion at 11000C. Figure 13.23 14-13

  14. Effect of Doping on Carrier Concentration • The mass action law: np = ni2 where ni (constant) is intrinsic concentration of carriers in a semiconductor. • Since the semiconductor must be electrically neutral Na + n = Nd + p where Na and Nd are concentrations of negative donor and positive acceptors. • In a n-type semiconductor, Na = 0 and n>>p hence nn = Nd and pn = ni2/nn=ni2/Nd np = ni2/pp = ni2/Na Table13.5 14-14

  15. Carrier Concentration • For Si at 300K, intrinsic carrier concentration ni=1.5 x 1016 carier/m2 • For extrinsic silicon doped with arsenic nn = 1021 electrons/m3 pn = 2.25 x 1011 holes/m3 • As the concentration of impurities increase , mobility of carriers decrease. Figure 13.26 14-15

  16. Effect of Temperature on Electrical Conductivity • Electrical conductivity increases with temperature as more and more impurity atoms are ionized. • Exhaustion range: temperature at which donor atom becomes completely ionized . • Saturation range: Acceptor atoms become completely ionized. • Beyond these ranges, temperature does not change conductivity substantially. • Further increase in temperature results in intrinsic conduction becoming dominant and is called intrinsic range. Figure 13.27 14-16

  17. Semiconductor Devices – pn Junction • pn junction if formed by doping a single crystal of silicon first by n-type and then by p type material. • Also produced by diffusion and impurities. • Majority carriers cross over the junction and recombine but the process stops later as electrons repelled by negative ions giving rise to depleted zones. • Under equilibrium conditions, there exists a barrier to majority carrier flow. Figure 13.29a Figure 13.30b 14-17

  18. Reverse and Forward Biased pn Junction • Reverse biased: n-type is connected to the positive terminal and p-type to negative. • Majority carrier electrons and holes move away from junction and current does not flow. • Leakage current flows due to minority carriers. • Forward biased: n-type is connected to negative terminal and p-type to positive. • Majority carriers are repelled to the junction and recombine and the current flows. Figure 13.32 Figure 13.33 Figure 13.31 14-18

  19. Application of pn Junction Diode • Rectifier Diodes: Converts alternating voltage into direct voltage (rectification). • When AC signal is applied to diode, current flows only when p-region is positive and hence half way rectification is achieved. • Signal can be further smoothened by using electronics. Figure 13.34 14-19

  20. Breakdown Diodes (Zener Diodes) • Zener diodes have small breakdown currents. • With application of breakdown voltage, in reverse bias, reverse current increases rapidly. • Electrons gain sufficient energy to knock more electrons from covalent bonds. • These are available for conduction in reverse bias. Figure 13.36 14-20

  21. Bipolar Junction Transistor • BJT consists of two pn junctions occurring sequentially on a single crystal. • Can serve as current amplifier. • Emitter: n-type emits electrons. • Base: p-type, o.1mm thick, controls flow of charge. • Collector: n-type, collects charge carrier. • Emitter base junction is forward biased and collector base junction is reverse biased. • Small base current can be used to control large collector current. Figure 13.37 Figure 13.38 14-21

  22. Microelectronics • Microelectronic planar bipolar transistors: Relatively large island of n-type silicon is formed first in silicon substrate. • Smaller island of p and n type silicon are created on larger n type island. Figure 13.39 14-22

  23. Microelectronic Planar Field-Effect Transistor • MOSFET: Metal oxide semiconductor field effect transistor – compact and cheap. • Two islands of n-type silicon are created in a substrate of p-type silicon. • Between n-type silicon of source and drain there is a p type region. • A surface layer of SiO2 is formed on the p region and another layer of polysilicon on SiO2 layer Figure 13.40 14-23

  24. MOSFET (Cont..) • Electrons will flow between source and drain if there is positive voltage difference between then. • MOSFET has capability of current amplification. Figure 13.41 14-24

  25. Fabrication of Microelectric Integrated Circuits • Photolithography: The process by which microscopic pattern is transferred from a photomask to the silicon wafer surface. • wafer is coated with photoresist. • Then exposed to ultra- violet light through photomask. • Pattern of photoresist is left where mask is transparent. • Wafer is immersed in hydrofluoric acid. • Photoresist pattern is removed by chemicals. Figure 13.45 14-25

  26. Diffusion Technique • Impurity atoms are diffused into silicon wafers at 11000C. • Thin silicon dioxide patterns serve as masks to prevent dopant atoms from penetrating into silicon. • High concentration of dopant is deposited near surface in predeposit step. • In drive-in diffusion step, the wafers are placed in high temperature furnace and necessary concentration of dopant atoms at particular depth is attained. Figure 13.46a 14-26

  27. Ion Implantation Technique • Carried out at room temperature. • Dopant atoms are ionized and accelerated to high energies through a high potential difference of 50-100 KV. • On striking, ions embed in Si. • Photoresist or SiO2 mask is used to mask desired regions. • Damage to Si lattice is caused but can be healed by annealing. Figure 13.46b 14-27

  28. MOS Integrated Circuit Fabrication • SiN4 is deposited by CVD. • Boron ions are implanted to suppress unwanted conduction. • SiO2 layer is grown in inactive regions. • SiN4 is removed by etchants. • Insulating layer is deposited on wafer by CVD. • Al is deposited on wafer. • Protective layer is deposited on entire surface. Figure 13.47 14-28

  29. Complimentary Metal Oxide Semiconductor (MOS) • CMOS: Circuits containing both types of MOSFETs (NMOS and PMOS). • Made by isolating all NMOS devices with islands of p-type material. • Used in LSI circuits in microprocessors and computer memories. Figure 13.49 14-29

  30. Compound Semiconductors • MX semiconductors are major semiconducting compounds. • As molecular mass increases energy band gap decreases and electron mobility increases. • Increased ionic bonding character causes energy bond gap to increase and electron mobility to decrease. • Example: Gallium arsenide: (GaAs) • Higher mobility • GaAs devices have better radiation resistance. Figure 13.49 14-30

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