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DAQ – pixel to backend readout

DAQ – pixel to backend readout. Contents Time schedule What was planned on 05.03.2007 Backup solutions What to do – test systems, etc. Conclusions What should the result of this discussion be? An understanding of what the plan is. There have been ideas, but how do these get realized ?

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DAQ – pixel to backend readout

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  1. DAQ – pixel to backend readout • Contents • Time schedule • What was planned on 05.03.2007 • Backup solutions • What to do – test systems, etc. • Conclusions • What should the result of this discussion be? • An understanding of what the plan is. • There have been ideas, but how do these get realized ? • An understanding of who does what. • Without planable manpower and money, nothing is going to happen ! • I’m interested as an end user – I’m clearly not going to build the interface. XFEL DAQ (CY)

  2. Time schedule • Basic milestones • 2007 start • Early 2008 test interfaces and test system • 2009 Small test system for use at SLAC • 2009+ prototype detector systems • 2012+ XFEL start • Need more precise information from HPAD, LSDD,… XFEL DAQ (CY)

  3. 05.03.2007 - frontend to backend hardware Idea: Each module interface sends 1/12 (36) frames concurrently to 12 switches. CPUs connected to the switches receive, 1 or more complete, frames. Xilinx Virtex FPGA RocketIO used with TCP to implement the interface connection. To avoid contention on the CPU links the frame ordering within the group of 36 must be defined – see next slide. Same datasize per event – no shaping required to optimize transmission. XFEL DAQ (CY)

  4. 05.03.2007 - frontend to backend timing Frame ordering within the group of 36 staggered between interfaces. Hopefully removes network contention. XFEL DAQ (CY)

  5. 05.03.2007 - frontend to backend • Challenges • Use of Rocket IO • FE has little experience of RocketIO on Virtex • Use of TCP • FE has no experience of TCP (or UDP) on Virtex • A plan is required …urgently • Schedule, design, manpower, money and test system. • Is a parallel backup development required? • Ensures that rollout time schedule commitments can be met • Does not have to have full size or performance XFEL DAQ (CY)

  6. Possible backups - 1 • RocketIO to TCP converter PC • Standard technique • Buffering on PC • TCP forwarding by PC • Raw RocketIO protocol • Requires PCI or similar PC board interface RocketIO … PC … TCP switch XFEL DAQ (CY)

  7. Possible backups - 2 • RocketIO to crate board • Raw RocketIO protocol • Board to crate CPU • Via backplane • CPU to PC • TCP forwarding interface RocketIO … backplane Crate … TCP switch XFEL DAQ (CY)

  8. What to do – test systems, etc. • A test system is required • During development • Bandwidth, retransmits, latencies, etc. • Must be realistic in scale to give predictive results w.r.t. final solution. • A timing system is required • During testing • To tag event latencies • During running • Again to tag events to monitor the final solution XFEL DAQ (CY)

  9. Conclusions • Decisions required – or maybe everything’s organized already ? • Specify final solution • Specify backup solution • Time schedule final+backup w.r.t. 3rd party requirements. • Manpower • How many people are required and who ? • Money • How much and how is the funding organized ? • etc. XFEL DAQ (CY)

  10. Reserve slides XFEL DAQ (CY)

  11. 05.03.2007 - frontend to backend connectivity interface wire/available time 1 2 …8 • HPAD • 2MB/frame • ~400 frames/train • 10 Hz rep. rate • Data transfer • 1Gbit/s links • Locked to inter-train period • Transfer to archive requires 10Gbit/s links and concentrators (big boxes) 75/100ms FL switch 1 2 …12 75/100ms FL PC …108 75/100ms SL switch 1 2 …12 9x75/900ms SL PC 1 2 …9 9x12x75/8100ms archiver 1 2 …9 Box multiplicity/layer XFEL DAQ (CY)

  12. Workplan • The following work activities can be identified. • Activity 1 • A frontend interface module is required. • Allows DESY to get experience of XiLinx/TCP-rocketIO. • Allows TCP throughput characteristics to FL PCs to be measured • Test system requirements are specified in the note. • The final frontend test module cannot be quickly available ! • Using PCs to emulate the interface is limited not having a realtime trigger. • A bused timing system is required. • Allows performance latencies to be measured • Can the LINAC timing system be used? • Both these systems should be useable in the final systems. XFEL DAQ (CY)

  13. Workplan • Activity 2 • A small size farm for testing FLASH software in a Farm • The same farm for developing software • Activity 1 could be built into this Farm • Activity 3 • A test stand to measure switch performance. • A test stand to measure PC performance. • A full work plan is required ! • Some suitable test equipment (switches+PCs) can be appropriated from ZEUS and other HERA experiments. XFEL DAQ (CY)

  14. Time schedule • Activities can be addressed in parallel • Key issues: • Proof that the TCP frontend interface works. • Proof that a full frontend to backend slice of the farm works. • Problems need to be identified as early as possible. • Basic milestones • 2007 start • Early 2008 final test interface • 2009 Small test system for use at SLAC • 2009+ prototype detector systems • 2012+ XFEL start XFEL DAQ (CY)

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