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COMP541 Datapath & Single-Cycle MIPS

COMP541 Datapath & Single-Cycle MIPS. Montek Singh Mar {5, 7}, 2018. Topics. Complete the datapath Add control to it Create a full single-cycle MIPS! Reading Chapter 7 Review MIPS assembly language Chapter 6 of course textbook Or, Patterson Hennessy (inside front flap). A MIPS CPU.

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COMP541 Datapath & Single-Cycle MIPS

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  1. COMP541Datapath &Single-Cycle MIPS Montek Singh Mar {5, 7}, 2018

  2. Topics • Complete the datapath • Add control to it • Create a full single-cycle MIPS! • Reading • Chapter 7 • Review MIPS assembly language • Chapter 6 of course textbook • Or, Patterson Hennessy (inside front flap)

  3. A MIPS CPU reset clk clk memwrite dataaddr readdata writedata pc Instr Memory MIPS CPU Data Memory instr

  4. Top-Level: MIPS CPU + memories reset clk Top-level module reset clk clk readdata writedata dataaddr memwrite pc Instr Memory MIPS CPU Data Memory instr We will add I/O devices (display, keyboard, etc.) later

  5. One level down: Inside MIPS • Datapath: components that store or process data • registers, ALU, multiplexors, sign-extension, etc. • we will regard memories as outside the CPU, so not part of the core datapath • Control: components that tell datapath what to do and when • control logic (FSMs or combinational look-up tables) Control opcode, func, flagZ… ALUFN,regwrite, regdst… writedata readdata dataadr memwrite clk pc Instr Memory MIPS Datapath Data Memory MIPS CPU reset instr clk

  6. Review: MIPS instruction types Three instruction formats: R-Type: register operands I-Type: immediate operand J-Type: for jumps

  7. Review: Instruction Formats

  8. R-Type instructions • Register-type • 3 register operands: • rs, rt: source registers • rd: destination register • Other fields: • op: the operation code or opcode (0 for R-type instructions) • funct: the function • together, op and funct tell the computer which operation to perform • shamt: the shift amount for shift instructions, otherwise itis 0

  9. R-Type Examples Note the order of registers in the assembly code: add rd, rs, rt

  10. I-Type instructions • Immediate-type • 3 operands: • op: the opcode • rs, rt: register operands • imm: 16-bit two’s complement immediate

  11. I-Type Examples Note the differing order of registers in the assembly and machine codes: addi rt, rs, imm lw rt, imm(rs) sw rt, imm(rs)

  12. J-Type instructions • Jump-type • 26-bit address operand (addr) • Used for jump instructions (j)

  13. Summary: Instruction Formats

  14. MIPS Design from Comp411 We will not be implementing the textbook version of MIPS in our labs. Instead, we will implement the MIPS design from Comp411, which has more features.

  15. Design Approach Our Bag of Components: Registers Muxes + ALU & adders A Instruction A B Memory D ALU WD Data A RA1 RA2 Memory RD 1 0 WA R/W Register Memories File WE (3-port) WD RD1 RD2 “Incremental Featurism” • We will implement circuits for each type of instruction individually, and merge them (using MUXes, etc). Steps: • 1. 3-Operand ALU instrs • 2. ALU w/immediate instrs • 2. Loads & Stores • 3. Jumps & Branches • 4. Exceptions (briefly)

  16. Review: The MIPS ISA 5 5 5 5 6 6 16 26 rs rt rd OP 000000 shamt func The MIPS instruction set as seen from a Hardware Perspective R-type: ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] rs rt immediate 001XXX I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) • Instruction classes • distinguished by types: • 3-operand ALU • ALU w/immediate • Loads/Stores • Branches • Jumps rs rt immediate 10X011 I-type: Load and Store Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] rs rt immediate 10X011 I-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) 26-bit constant 00001X J-type: jump PC  (PC & 0xf0000000) | 4*(immediate)

  17. Fetching Sequential Instructions + 4 32 32 32 32 P C Read Address Instruction register Instruction Memory We will talk about branches and jumps later.

  18. Instruction Fetch/Decode Control Logic CONTROL SIGNALS • Use a counter to FETCH the next instruction: • PROGRAM COUNTER (PC) • use PC as memory address • add 4 to PC, load new value at end of cycle • fetch instruction from memory • use some instruction fields directly (register numbers, 16-bit constant) • decode rest of the instruction • use bits <31:26> and <5:0> to generate controls PC 00 Instruction A 32 Memory D +4 32 32 INSTRUCTION WORD FIELDS OP[31:26], FUNC[5:0]

  19. 3-Operand ALU Data Path 00 Instruction A Memory D +4 Rs: <25:21> rs rt rd 000000 Control Logic WERF! 00000 100XXX R-type: ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] PC Rt: <20:16> RA1 Register RA2 Rd: <15:11> WD WA File WERF RD1 RD2 WE 32 32 A B ALU ALUFN ALUFN WERF 32

  20. Shift Instructions 00 Instruction A Memory D +4 rs rt rd 000000 Control Logic 0 1 shamt 000XXX R-type: ALU with Register operands sll: Reg[rd]  Reg[rt] (shift) shamt sllv: Reg[rd]  Reg[rt] (shift) Reg[rs] PC Rt: <20:16> Rs: <25:21> RA1 Register RA2 Rd: <15:11> WD WA File WERF RD1 RD2 WE shamt:<10:6> ASEL A B ALU ALUFN ASEL! ALUFN WERF 32 ASEL

  21. ALU with Immediate rs rt immediate 001XXX 00 Instruction I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) A Memory D +4 Rs: <25:21> WERF Rd:<15:11> 0 1 Rt:<20:16> 0 1 1 0 Control Logic shamt:<10:6> ASEL SEXT ALUFN WERF PC Rt: <20:16> BSEL Register RA1 RA2 WD WA WA File RD1 RD2 WE imm: <15:0> SEXT BSEL • How do you build SEXT? • 1  pad with sign • 0  pad with 0s SEXT A B ALU BSEL! BSEL ALUFN ASEL

  22. Load Instruction 00 Instruction A Memory D +4 Rs: <25:21> Rd:<15:11> WERF 0 1 Rt:<20:16> BSEL 0 1 0 1 Control Logic shamt:<10:6> ASEL BSEL R/W ALUFN ALUFN WERF rs rt 100011 immediate I-type: Load Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] PC Rt: <20:16> BSEL Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> SEXT SEXT SEXT A B ALU Wr WD WDSEL Data Memory Wr Adr RD 32 ASEL 32 0 1 2 WDSEL

  23. Store Instruction 00 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> 0 1 Rt:<20:16> BSEL 1 0 0 1 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD WERF 0 1 2 WDSEL rs rt immediate 101011 I-type: Store Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] PC Rt: <20:16> BSEL Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> 32 No WERF! A B SEXT ALU ASEL

  24. JMP Instructions 00 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> Rt:<20:16> BSEL 1 0 1 0 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL PC<31:28>:J<25:0>:00 26-bit constant 00001X J-type: j: PC  (PC & 0xf0000000) | 4*(immediate) jal: PC  (PC & 0xf0000000) | 4*(immediate); Reg[31]  PC + 4 PCSEL 3 2 1 0 PC Rt: <20:16> WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD 31 WA WA File RD1 RD2 WE Imm: <15:0> PCSEL A B SEXT ALU WERF ASEL PC+4 32

  25. BEQ/BNE Instructions 00 Instruction A Memory D +4 Rs: <25:21> WASEL WERF Rd:<15:11> 31 Rt:<20:16> BSEL 1 0 0 1 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL PC<31:28>:J<25:0>:00 rs rt 00010X immediate BT PCSEL 3 2 1 0 R-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC + 4 + 4*SEXT(immediate) PC That “x4” unit is trivial. I’ll just wire the input shifted over 2–bit positions. Rt: <20:16> J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> Z x4 + Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction. PCSEL BT A B SEXT ALU Z WERF ASEL PC+4 32

  26. Jump Indirect Instructions 00 Instruction A Memory D +4 Rs: <25:21> WASEL WERF Rd:<15:11> rs rt rd 31 000000 Rt:<20:16> BSEL 1 0 1 0 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL 00000 00100X PC<31:28>:J<25:0>:00 BT JT PCSEL 3 2 1 0 R-type: Jump Indirect, Jump and Link Indirect jr: PC  Reg[rs] jalr: PC  Reg[rs], Reg[rd]  PC + 4 PC Rt: <20:16> J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> JT Z x4 + PCSEL BT A B SEXT ALU Z WERF ASEL PC+4 32

  27. Comparisons 00 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> Rt:<20:16> BSEL 1 0 0 1 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL rs rt 00101X immediate PC<31:28>:J<25:0>:00 BT JT I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 PCSEL 3 2 1 0 PC NOTE: Sign-extension done for both! WHY?? But ALUFN is unsigned comparison (LTU) for sltiu. Rt: <20:16> WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA 31 File RD1 RD2 WE Imm: <15:0> JT Z x4 + PCSEL BT A B SEXT ALU Z WERF ASEL PC+4 32

  28. More comparisons 00 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> rs rt rd 000000 Rt:<20:16> BSEL 0 1 1 0 SEXT Control Logic SEXT shamt:<10:6> ASEL Wr BSEL WD R/W ALUFN WDSEL WASEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL 00000 10101X PC<31:28>:J<25:0>:00 BT JT R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 sltu: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 PCSEL 3 2 1 0 PC Rt: <20:16> WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA 31 File RD1 RD2 WE Imm: <15:0> JT Z x4 + PCSEL BT A B SEXT ALU Z WERF ASEL PC+4 32

  29. LUI 00 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> Rt:<20:16> BSEL 1 0 Control Logic Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL rt 00000 001111 immediate PC<31:28>:J<25:0>:00 BT JT I-type: Load upper immediate lui: Reg[rt]  Immediate << 16 PCSEL 3 2 1 0 PC Rt: <20:16> WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD WA WA 31 File RD1 RD2 WE Imm: <15:0> SEXT JT SEXT Z x4 shamt:<10:6> + “16” ASEL 0 1 2 PCSEL BT WASEL A B SEXT ALU Z WERF ASEL PC+4 32

  30. All put together… 00 Instruction A Memory D +4 Rs: <25:21> WERF Rd:<15:11> Rt:<20:16> BSEL 1 0 Control Logic Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL PC<31:28>:J<25:0>:00 BT JT PCSEL 3 2 1 0 PC Rt: <20:16> WASEL J:<25:0> 0 1 2 Register RA1 RA2 WD 31 WA WA File RD1 RD2 WE Imm: <15:0> SEXT JT SEXT Z x4 shamt:<10:6> + “16” ASEL 0 1 2 PCSEL BT WASEL A B SEXT ALU Z WERF ASEL PC+4 32

  31. Reset, Interrupts, and Exceptions • Upon reset/reboot: • Need to set PC to where boot code resides in memory • Interrupts/Exceptions: • any event that causes interruption in program flow • FAULTS: e.g., nonexistent opcode, divide-by-zero • TRAPS & system calls: e.g., read-a-character • I/O events: e.g., key pressed • How to handle? • interrupt current running program • invoke exception handler • return to program to continue execution • Registers $k0, $k1 ($26, $27) • reserved for operating system (kernel), interrupt handlers • any others used must be saved/restored

  32. Exceptions 00 PCSEL 6 5 4 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WASEL WERF 0 1 2 3 Rd:<15:11> 31 27 Rt:<20:16> BSEL 1 0 Control Logic shamt:<10:6> “16” ASEL 0 1 2 Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL 0x80000000 Reset: PC  0x80000000 PC<31:28>:J<25:0>:00 0x80000040 BT 0x80000080 JT Bad Opcode: Reg[27]  PC+4; PC  0x80000040 IRQ: Reg[27]  PC+4; PC  0x80000080 PC Rt: <20:16> J:<25:0> Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> RESET SEXT JT SEXT Z IRQ x4 + PCSEL BT WASEL A B SEXT ALU Z WERF ASEL PC+4 32

  33. Our Lab version: three changes No support for exceptions Supports Reset: PC starts over at 0x0040_0000 address chosen for compatibility with MARS assembler Supports Enable: Freezes when Enable = 0 will allow us to “single-step” through execution debugging aid

  34. Support for Reset 00 PCSEL 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WASEL WERF 0 1 2 Rd:<15:11> 31 Rt:<20:16> BSEL 1 0 Control Logic shamt:<10:6> “16” ASEL 0 1 2 Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL • “Reset” input: starts PC over at 0x0040_0000 • address chosen for compatibility with MARS assembler PC<31:28>:J<25:0>:00 BT JT PC On Reset: PC  0x0040_0000 RESET Rt: <20:16> J:<25:0> Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> SEXT JT SEXT Z x4 + PCSEL BT WASEL A B SEXT ALU Z WERF ASEL PC+4 32

  35. Support for Enable 00 PCSEL 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WASEL WERF 0 1 2 Rd:<15:11> 31 Rt:<20:16> BSEL 1 0 Control Logic shamt:<10:6> “16” ASEL 0 1 2 Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL • “Enable” input: Enable = 0 disables the processor • disables writes to: PC, register file and data memory PC<31:28>:J<25:0>:00 BT JT On Reset: PC  0x0040_0000 PC RESET Rt: <20:16> ENABLE J:<25:0> Writes disabledby controller Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> SEXT JT SEXT Z x4 + PCSEL BT WASEL A B SEXT ALU Z WERF ASEL PC+4 32

  36. MIPS: Our Final Version 00 PCSEL 3 2 1 0 Instruction A Memory D +4 Rs: <25:21> WASEL WERF 0 1 2 Rd:<15:11> 31 Rt:<20:16> BSEL 1 0 Control Logic shamt:<10:6> “16” ASEL 0 1 2 Wr BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL This is a complete 32-bit processor. Although designed in “one” class lecture,it executes the majority of theMIPS R2000 instruction set. PC<31:28>:J<25:0>:00 BT JT PC Executes one instruction per clock Rt: <20:16> ENABLE J:<25:0> RESET Register RA1 RA2 WD WA WA File RD1 RD2 WE Imm: <15:0> SEXT JT SEXT Z x4 + PCSEL BT WASEL A B SEXT ALU Z WERF ASEL PC+4 32

  37. Our MIPS: Top-level hierarchy 00 Instruction A Memory D +4 Rs: instr<25:21> WERF Rd: instr<15:11> Rt: instr<20:16> BSEL 1 0 Control Logic BSEL WD R/W ALUFN WDSEL Data Memory ALUFN Wr Adr RD 0 1 2 WDSEL PC<31:28>:J<25:0>:00 BT JT PCSEL 3 2 1 0 newPC pcPlus4 MIPS CPU ENABLE PC pc[31:0] Datapath pc instr Rt: instr<20:16> WASEL J: instr<25:0> reg_writeaddr RESET 0 1 2 Register RA1 RA2 reg_writedata WD WA WA 31 File RD1 RD2 WE ENABLE ReadData2 ReadData1 SEXT Imm: instr<15:0> op: instr<31:26> Z JT SEXT func: instr<5:0> signImm <<2 shamt: instr<10:6> + “16” ASEL mem_writedata 0 1 2 PCSEL BT aluB aluA WASEL A B SEXT mem_wr ALU Wr mem_addr Z WERF alu_result ASEL mem_readdata (PC+4) pcPlus4 32

  38. Make design modular • Follow hierachy specified • Small amounts of logic can be “inlined” (instead of separate module) • e.g.: muxes, sign extension, adders, shift-by-2

  39. Summary • We learned about a complete MIPS CPU • NOTE: Many details in textbook are different… • … from what you will implement in the lab • our lab MIPS has more features

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