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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Day 19: October 22, 2010 Pass Transistor Logic. Today. Pass Transistor Logic Muxes Performance Composition Logic Tristates. Behavior. O=S*A + S*/B. S. A. B. Delay. Assume R 0 /2 drive 10C 0 load

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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

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  1. ESE370:Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 22, 2010 Pass Transistor Logic

  2. Today • Pass Transistor Logic • Muxes • Performance • Composition • Logic • Tristates

  3. Behavior • O=S*A + S*/B S A B

  4. Delay • Assume R0/2 drive • 10C0 load • What else need to know? • Cdiff=CSB or CDB • Assume Cdiff≈Cgate 5 2 5

  5. Day 10 Capacitances • GS, GB, GD, SB, DB, SD

  6. Day 10 Contact Capacitance • n+ contacts are formed by doping = diffusion • Depletion under contact • Contact-Body capacitance • Depletion around perimeter of contact • Also contact-Body capacitance

  7. Day 10 Contact/Diffusion Capacitance • Cj – diffusion depletion • Cjsw – sidewall capacitance • LS – length of diffusion LS

  8. Delay 5 2 5

  9. Delay

  10. CMOS Equivalent

  11. CMOS Delay • O=S*A + S*/B

  12. What’s different? • What’s different about the output?

  13. Output ok? • Is the output usable?

  14. CMOS DC Transfer Function

  15. After CMOS Inverter

  16. What does this do?

  17. Cascade Functional?

  18. Voltage Drop • Voltage drop across any number of series transistors is one Vth • Think about two series transistors as one transistor of twice the length

  19. Day 9 Pinch Off • When voltage drops below VT, drops out of inversion • Occurs when: VGS-VDS< VT • Conclusion: • current cannot increase with VDS once VDS> VGS-VT • current must adjust so that VDS= VGS-VT • If current dropped to zero, then would invert and conduct again…

  20. Performance? • Assume R0/2 drive • 10C0 load • Cdiff=Cgate 5 2 5

  21. What does this do? A B

  22. Performance • R0/2 drive • 10C0 load 5 2 5

  23. Performance • R0/2 drive • 10C0 load

  24. Not Isolating • Does not isolate downstream capacitive load • Stage delay now dependent on downstream stages

  25. Class Ended Here

  26. Power Implications • What’s the power impact of partial swing?

  27. Back to Rail • How make it go to rail?

  28. Transmission Gate

  29. Level Restorer

  30. Level Restorer

  31. Level Restore • What issue arises here?

  32. Level Restore • What issue arises here?

  33. Tristate • Sometimes want to be able to not drive a line • Bus driven from different places • I/O port – sometimes read, sometime write

  34. Tristate Driver

  35. Tri-State Drivers

  36. Next week • No new assignment now • (will get new one after midterm) • Class Monday • Midterm Wednesday • No lecture • Midterm 7-9pm in this room • Class Friday

  37. Midterm(Everything through today) • Restoration • Implement or identify gate / logic function • Estimate performance for circuit • Estimate/reduce energy for circuit • Size transistors in gate/netlist • Variation impact • Scaling • Ratio and pass tr circuits fair game • Synchronous/clocking not on midterm

  38. Ideas • There are other logic disciplines • We have the tools to analyze • Pass Transistor Logic • Possibly smaller, faster • Not rail-to-rail • Techniques to restore • Cascading without buffering  slow • Tristate Drivers

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