Fundamentals on Testing and Design for Testability

1. Fundamentals on Testing and Design for Testability

2. Design Verification, Testing and Diagnosis • Design Verification: Ascertain the design perform its specified behavior • Testing: Exercise the system and analyze the response to ascertain whether it behaves correctly • Diagnosis: To locate the cause of misbehavior after the incorrect behavior is detected

3. Some Real Defects in Chips • Processing Faults • missing contact windows • parasitic transistors • oxide breakdown • Material Defects • bulk defects (cracks, crystal imperfections) • surface impurities (ion migration) • Time-Dependent Failures • dielectric breakdown • electromigration • Packaging Failures • contact degradation • seal leaks

4. Faults, Errors and Failures • Fault: A physical defect within a circuit or a system • May or may not cause a system failure • Error: Manifestation of a fault that results in incorrect circuit (system) outputs or states • Caused by faults • Failure: Deviation of a circuit or system from its specified behavior • Fails to do what it should do • Caused by an error • Fault ---> Error ---> Failure

5. Scenario for Manufacture Test TEST VECTORS MANUFACTURED CIRCUIT CIRCUIT RESPONSE CORRECT RESPONSES COMPARATOR PASS/FAIL

6. 1000 500 100 Cost 50 per 10 fault (Dollars) 5 1 0.5 IC Board System Warranty Test Test Test Repair Purpose of Manufacture Testing • Verify Manufacture of Circuit • Improve System Reliability • Diminish System Cost • Cost of repair goes up by an order of magnitude each step away from fab line B. Davis, The Economics of Automatic Testing , McGRAW-HILL, 1982.

7. Testing and Quality Shipped Parts ASIC Testing Fabrication Yield: Quality: Fraction of Defective parts good parts per million (DPM) Rejects * Quality of shipped part is a function of yield Y and the test (fault) coverage T.

8. # of detected faults T = # of possible faults Fault Coverage * Fault coverage T is the measure of the ability of a set of tests to detect a given class of faults that may occur on the device under test.

9. (1- T ) DL = 1 - Y Defect Level * Defect Level, DL is the fraction of the shipped parts that are defective. Y: yield T: fault coverage

10. 1 Y=.01 (1-T) .9 DL = 1 - Y Y = Yield .8 Y=.10 .7 .6 Y=.25 .5 .4 Y=.50 .3 Y=.75 .2 Y=.90 .1 Y=.99 0 0 10 20 30 40 50 60 70 80 90 100 Fault Coverage, T (%) Relating Defect Level to Fault Coverage

11. Defect Level, Yield and Fault Coverage Yield Fault Coverage DPM 50% 90% 67,000 75% 90% 28,000 90% 90% 10,000 95% 90% 5,000 99% 90% 1,000 90% 90% 10,000 90% 95% 5,000 90% 99% 1,000 90% 99.9% 100

12. ASIC • What is ASIC: Application Specific Integrated Circuits • Why we need ASICs • Microelectronic economics • Volume • Time to market • Quality

13. ASICs' Demand * While ASIC density and complexity have exploded, global market pressures have increased the demand for both Quality and Quick Turnaround .

14. 40 35 30 25 20 15 10 Measured development times Extrapolated curve 5 0 20 40 60 80 100 Controllability and observability as a percentage of circuit covered Test Development Time vs. Testability

15. Growth Stagnation Decline Lost revenue due to delay Time Delay in reaching market Time-to-Market Model * 1/8 delay of the product 1/3 lifetime reduces revenue.

16. Why Testing is Difficult ? • Test application time can be exploded for exhaustive testing of VLSI • For a combinational circuit with 50 inputs, we need 250 = 1.126x1015 test patterns. Assume one test per 10-7sec, it takes 1.125x108sec = 3.57yrs. to test such a circuit. • Test generation of sequential circuits are even more difficult. • Lack of Controllability and Observability ofFlip-Flops (Latches) • Functional testing may not be able to detect the physical faults

17. How To Do Test • Fault Modeling • Identify target faults • Limit the scope of test generation • Make analysis possible • Test Generation • Automatical or Manual • Fault Simulation • Assess completeness of tests • Testability Analysis • Analyze a circuit for potential problem on test generation • Design For Testability • Design a circuit for guaranteed test generation • Introduce both area overhead and performance degradation

18. The New Challenges for VLSI Testing • Chip, Board, Module & System for high • Performance • Density • Integration • Reliability

19. Reference: • 《Digital Systems testing and testable design》 ISBN：0－7167－8179－4 Author：Breuer mELVIN a. etc • 《VLSI Testing digital and mixed analogure/digital techinques》 ISBN：085296 901 5 Author：Stanley Lhurst

20. DEC Alpha Chip (1994) * 64-bit RISC * 200 MHz * 400 MIPS * 200 Mflops * 16.8*13.9-mm die * 1.68 million Txs * 431-pin package * 3.3-V * 30W power consumption.

21. Multi-Chip Module (MCM) * IBM Enterprise System/9000* Type 9121 Model 320 * Air-Cooled Processor Technology * Integration of bipolar chips, CMOS SRAM chips, and ECL & DCS logic circuitry in a TCM (thermal conduction module) (Ref: IBM J. RES. DEVELOP., May 1991)

22. Wafer Scale Integration (WSI) * ELSA (European Large SIMD Array), a wafer-scale two-dimensional array of single-bit processors * MUSE (Matrix Update Systolic Experiment), MIT Lincoln Laboratory

23. Traditional Design Flow • Conduct testing after design Yes Too LargeorToo Slow? DesignforTestability No Design Spec. Design Testability Analysis TestabilityImprovement? No Yes Done

24. The Infamous Design/Test Wall 30 years of experience proves that test after design does not work! Oh no! What does Functionally correct! this chip do?! We're done! Design Engineering Test Engineering

25. TESTABILITY New Design Mission • Design circuit to optimally satisfy or trade-off their design constraints in terms of area, performance and testability. PERFORMANCE AREA

26. Design Function/ Satisfied Spec. Behavior ? Test plan Testable Design ATPG Rules TESTS Testability Analysis MASK New VLSI Design Flow No Yes Logic Structure Synthesis Circuit Synthesis Placement/ Routing

27. Why Model Faults ? • I/O function tests inadequate for manufacturing • Functionality vs. component & interconnection testing • Exhaustive testing is Prohibitively expensive

28. Why Model Faults ? • Fault model identifies target faults • Model faults most likely to occur • Fault model limits the scope of test generation • Creat tests only for the modeled faults • Fault model makes effectiveness measurable by experiments • Fault coverage can be computed for specific test patterns to reflect its effectiveness • Fault model makes analysis possible • Associate specific defects with specific test patterns

29. Fault Modeling Modeling the effects of physical defects on the logic function and timing. • Physical Defects: • Silicon Defects • Photolithographic Defects • Mask Contamination • Process Variations • Defective Oxide

30. Fault Modeling (cont'd) • Electrical Effects: • Shorts (Bridging Faults) • Opens • Transistor Stuck-On/Open • Resistive Shorts and Opens • Change in Threshold Voltages • Logic Effects: • Logic Stuck-At-0/1 • Slower Transition (Delay Faults) • AND-Bridging, OR-Bridging

31. Fault Modeling * Stuck-At Faults * Bridging Faults * Transistor Stuck-On/Open Faults * IDDQ Faults * Functional Faults * Memory Faults * PLA Faults * Delay Faults * State Transition Faults

32. Faulty Response Test Vector True Response 0 0 1/0 1 1 1/0 1 stuck-at-0 Single Stuck-At Faults • Only one line is faulty. • Faulty line permanently set to 0 or 1. • Fault can be at an input or output of a gate. Assumptions:

33. Multiple Stuck-At Faults • Several stuck-at faults occur at the same time • Important in high density circuits • For a circuit with k lines • there are 2k single stuck-at faults • there are 3k-1 multiple stuck-at faults

34. Why Single Stuck-At Fault Model? * Complexity is greatly reduced. Many different physical defects may be modeled by the same logical single stuck-at fault. * Single stuck-at fault is technology independent. Can be applied to TTL, ECL, CMOS, etc. * Single stuck-at fault is design style independent. Gate Arrays, Standard Cell, Custom VLSI * Even when single stuck-at fault does not accurately model physical defects, the tests derived for logic faults are still valid for these defects. * Single stuck-at tests cover a large percentage of multiple stuck-at faults.

35. Multiple Faults • Multiple Stuck-fault coverage by single-fault tests of combinational circuit: • 4-bit ALU (Hughes & McCluskey, ITC-84)All double and most triple-faults covered. • Large circuits (Jacob & Biswas, ITC-87)Almost 100% multiple faults covered for circuits with 3 or more outputs. • No results available for sequential circuits.

36. A B A f g B Bridging Faults • Two or more normally distinct points (lines) are shorted together • Logic effect depends on technology • Wired-AND for TTL • Wired-OR for ECL • CMOS ? f A f g B g A f B g

37. IDDQ ? 0 stuck-on * Transistor stuck-on may cause ambiguous logic level. * When input is low, both P and N transistors are conducting causing increased quiescent current, called IDDQ fault. CMOS Transistor Stuck-ON • depends on the relative impedances of the pull-up & pull-down networks

38. stuck-open ? = previous state 0 CMOS Transistor Stuck-OPEN * Transistor stuck-open may cause output floating.

39. Initialization stuck-open vector 1 0/0 0 0 1 memory behaviour CMOS Transistor Stuck-OPEN (cont'd) • Can turn the circuit into a sequential one • Stuck-open faults require two-vector tests

40. 100 stuck faults only 80 stuck and open faults 60 40 20 0 1000 2000 3000 Test Vectors Fault Coverage in a CMOS Chip

41. Summary of Stuck-Open Faults * First report: Wadsack, Bell Syst. Tech. J., 1978 * Recent results: Woodhall, et al, ITC-87 Experiment with 1-micron CMOS chips: • 4552 chips passed parametric test • 1255 chips (27.57%) failed tests for stuck-at faults • 44 chips (0.97%) failed tests for stuck-open faults • 4 chips with stuck-open faults passed tests for stuck-at faults Conclusion • Stuck-at faults are about 29 times more frequent than stuck-open faults • About 91% of chips with stuck-open faults may also have stuck-at faults • Faulty chips escaping tests for stuck-at faults = 0.121%

42. Functional Faults * Fault effects modeled at a higher level than logic for function modules, such as Decoders Multiplexers Adders Counters RAMs ROMs

43. AB A 2-bit Decoder AB AB B AB Functional Faults of Decoder f(Li/Lj): Instead of line Li, Line Lj is selected f(Li/Li+Lj ): In addition to Li, Lj is selected f(Li/0): None of the lines are selected

44. Memory Faults • Parametric Faults • Output Levels • Power Consumption • Noise Margin • Data Retention Time • Functional Faults • Stuck Faults in Address Register, Data Register, and Address Decoder • Cell Stuck Faults • Adjacent Cell Coupling Faults • Pattern-Sensitive Faults

45. 0 0 0 0 d b 0 a 0 Memory Faults • Pattern-sensitive faults: the presence of a faulty signal depends on the signal values of the nearby points • Most common in DRAMs • Adjacent cell coupling faults • Pattern sensitivity between a pair of cells a=b=0 => d=0 a=b=1 => d=1

46. 2 e . g . A pattern sensitive test is 5 n long for an n - bit RAM . Memory Testing * Test sequences can be derived without much difficulty for each specific fault. However, the length of the test sequence can be prohibitive. • Testing a 1-M bit chip at 10 ns per pattern would take 14 hours. • For a 64-M bit chip it would take 6 years.

47. PLA Faults * Stuck Faults * Crosspoint Faults Extra/Missing Transistors * Bridging Faults * Break Faults

48. A B C f1 f2 A B C P1 P1 f1 P2 f2 P2 AND-Array OR-Array Stuck Faults in PLA * S-A-0 & S-A-1 on inputs, input invertors, product lines, and outputs * Easy to simulate in gate model Gate-level representation

49. A B C A B C f1 f2 Growth s-a-1 s-a-0 f1 f2 Disappearance Missing Crosspoint Faults in PLA * Missing crosspoint in AND-array -- Growth fault * Missing crosspoint in OR-array -- Disappearance fault Equivalent stuck fault representation

50. A B C A B C f1 f2 f1 f2 Disapp. "0" Shrinkage "1" Appearance Extra Crosspoint Faults in PLA * Extra crosspoint in AND-array -- Shrinkage or disappearance fault * Extra crosspoint in OR-array -- Appearance fault Equivalent stuck fault representation