STRUCTURED LOGIC DESIGN WITH VHDL

1. STRUCTURED LOGIC DESIGN WITH VHDL Author: Nikola Jevtović Computer Science DepartmentSchool of Electrical EngineeringUniversity of Belgradeemail: jevtovic.nikola@gmail.com

2. Reference: “Structured Logic Design With VHDL” James R. Armstrong, F. Gail GrayVirginia Tech Structured Logic Design with VHDL

3. Chapter 1 Structured Design Concepts Structured Logic Design with VHDL

4. Structured Design Concepts The abstraction hierarchy can be expressed in two domains: • Structural domain: A domain in which a component is described in terms of interconnection of more primitive components. • Behavioral domain: A domain in which a component is described by defining its I/O response. Structured Logic Design with VHDL

5. Structured Design Concepts • Level of detail commonly used in design Structured Logic Design with VHDL

6. Structured Design Concepts Silicon level Circuit level Gate level Structured Logic Design with VHDL

7. Structured Design Concepts Register level Chip level System level Structured Logic Design with VHDL

8. Structured Design Concepts • Textual vs. Pictorial Representations Example of pictorial representations of logical circuits State Table State Assignment …also timing diagrams and/or truth tables (K-maps). Structured Logic Design with VHDL

9. Structured Design Concepts • Textual vs. Pictorial Representations Common textual methods are: • natural language (e.g. English), • equations (Boolean or differential) and • computer languages (hardware description language -HDL) Text is better for representing complex behavior; pictures are better for illustrating interrelationships. Structured Logic Design with VHDL

10. Structured Design Concepts • Types of behavioral descriptions • Algorithmic : the procedure defining the I/O response is not meant to imply any particular physical implementation. • Data flow : the data dependencies in the description match those in real implementation. Both are HDL implementations of behavior at the register and chip levels. Structured Logic Design with VHDL

11. Structured Design Concepts • Design process Logic synthesis Natural language (System level) Logic (Gate level) Natural language synthesis Algorithmic (Chip level) Circuit (Circuit level) Layout synthesis Algorithmic synthesis Data Flow (Register level) Geometrical Shapes (Layout level) Structured Logic Design with VHDL

12. Structured Design Concepts • Structural design decomposition Bottom-up design Top-down design Partial tree design Full tree design Behavioral modeling Structured Logic Design with VHDL

13. Chapter 2 Design Tools Structured Logic Design with VHDL

14. Design Tools • Editors (textual or graphic) • Simulators (stochastic or deterministic) • Checkers and Analyzers • Optimizers and Synthesizers Structured Logic Design with VHDL

15. Design Tools • Schematic editor: An editor which can be used to create and display an interconnected set of graphic tokens. • It has following features: • A library of primitive symbols. • A system of graphic windows (used to create an interconnect of graphic tokens). • Commands for creating wirelists. Structured Logic Design with VHDL

16. R D CLK D Q D Q Q CLK R R Graphical representation Digital device Design Tools • Simulator: A program which models the response of a system stimuli. • Process: A computational entity which models the function and delay of the digital device. process (CLK,R) begin if R=‘0’ then Q <= ‘0’; elsif CLK’EVENT and CLK=‘1’ then Q <= D; end if; end process; VHDL process Structured Logic Design with VHDL

17. Chapter 3 Basic Features of VHDL Structured Logic Design with VHDL

18. A basic element of a VHDL description is the block. architectureBLOCK_STRUCTURED ----- ----- -- Outer Block Declaration Section begin ----- ----- -- Outer Block Executable Statements A:block --- --- -- Inner Block A Declaration Section begin --- --- -- Inner Block A Executable Statements --- end blockA; endBLOCK_STRUCTURED; Basic Features of VHDL Structured Logic Design with VHDL

19. Basic Features of VHDL • Lexical description Character Set: • Upper case letters: A … Z • Digits: 0 … 9 • Special characters: “ # & ‘ ( ) * + , - . / : ; < = > _ | • Space character: (20) • Format effectors: • Carriage return: (0D) • Line feed: (0A) • Form feed: (0C) • Horizontal tabulation: (09) • Vertical tabulation: (0B) • Lower case letters: a… z • Other special characters: ! $ % @ ? [ \ ] ^ ` { } ~ Structured Logic Design with VHDL

20. Delimiters –characters that are used to separate lexical elements and have specific meanings in the language: & ‘ ( ) * + , - . / : ; < = > | Compound delimiteris a sequence of two delimiters that have special meanings: => ** := /= >= <= <> -- Basic Features of VHDL Structured Logic Design with VHDL

21. Basic Features of VHDL • Reserved words Structured Logic Design with VHDL

22. Basic Features of VHDL • Classification of Data Types: • Scalar (their values are single entities) • Enumeration – discrete • Integer – discrete, numeric • Physical – numeric • Floating point (or real – numeric) • Composite (their values are complex objects) • Array – all elements have the same type • Record – elements may have different types • Access (provide access to other types) • File (provide access to other files) Structured Logic Design with VHDL

23. Basic Features of VHDL • Classes of Objects • Constant– An object whose value is specified at compile and cannot be changed during simulation. • Variable– A data object whose current value can be changed by VHDL statements. • Signal– A data object that has a time dimension. Using waveforms, future values can be assigned without affecting the current value. Structured Logic Design with VHDL

24. Basic Features of VHDL • Declaration of Data Objects • Declaration of Constants constantconst_name:type_name:=const_value; • Declaration of Variables variablevar_name:type_name:=init_value; • Declaration of Signals signalsig_name:type_name:=init_value; Structured Logic Design with VHDL

25. Basic Features of VHDL • Assignment Statements • A Variable Assignment Statement A variable instantaneously replace its current value by a new value: var_name:=new_var_value; • A Signal Assignment Statement A new value of a signal is scheduled to occur at some future time. The current value is never changed: sig_name<=‘sig_value’ afterint_valuens; If not specified, the default value of time is delta time (infinitesimally small value of time in the future). Structured Logic Design with VHDL

26. priority Basic Features of VHDL • Operators in VHDL • Logical: and or nand nor xor • Relational: = /= < <= > => • Adding: + - & • Signing: + - • Multiplying: * / mod rem • Miscellaneous: ** abs not lowest highest Structured Logic Design with VHDL

27. Basic Features of VHDL • Sequential Control Statements • Wait statement wait onobjectuntilexpressionforintns; wait on X,Y until Z=0 for 100ns; wait for 100ns; wait on A,B,C; wait on A,B,C for 100ns; wait until Z=0; wait on X,Y until Z=0; Structured Logic Design with VHDL

28. Basic Features of VHDL • Sequential Control Statements • If Statement if{condition1}then {sequence_of_statements_1} elsif{condition2}then {sequence_of_statements_2} … … else{sequence_of_statements_n} end if; if A < 0 then LEVEL := 1; elsif A > 10 then LEVEL := 3; else LEVEL := 2; end if; Structured Logic Design with VHDL

29. Basic Features of VHDL • Sequential Control Statements • Case Statement case{expression}is when{choices_1} =>{sequence_of_statements_1} when{choices_2}=>{sequence_of_statements_2} … … when others =>{sequence_of_statements_n} end case; case A+B is when 0 => X <= “ZERO”; when (1 to 20) => X <= “POSITIVE”; when others => X <= “NEGATIVE”; end case; Structured Logic Design with VHDL

30. Basic Features of VHDL • Sequential Control Statements • Loop Statement -- FOR loop forNAMEin{range}loop {sequence_of_statements} end loop; for I in 1 to 10 loop A(I) := A(I) + 1; end loop; -- WHILE loop while{condition}loop {sequence_of_statements} end loop; while A<B loop A := A=1; end loop; -- Simple loop loop {sequence_of_statements} end loop; loop compute (x); exit when x<10; end loop; Structured Logic Design with VHDL

31. Basic Features of VHDL • Sequential Control Statements • Next Statement next{loop_label} [whencondition] • Exit Statement exit{loop_label} [whencondition] • Null Statement Does nothing, but it’s mandatory in “case” statements if no action is desired for certain choices – because all choices must be covered! Structured Logic Design with VHDL

32. Basic Features of VHDL • Concurrent Statements • -NOT executed in the order written; only when signal that affect the value computed by the statement changes; • -Plus, executed onceat the beginning of simulation; • Some statement types are both concurrent and sequential; Structured Logic Design with VHDL

33. Basic Features of VHDL • Concurrent Statements • Process Statement LABEL:process(sensitivity_signal_list){constant_declarations}{var_declarations}begin{sequential_statements}end processLABEL; LABEL: (sensitivity_signal_list) • Fundamental statement type; • All other concurrent statements can be written as processes; • Label and sensitivity list are optional; • Executed once at the beginning of simulation and when any signal in sensitivity list changes; Structured Logic Design with VHDL

34. Basic Features of VHDL • Concurrent Statements • Process Statement • If there is no sensitivity list, process will execute once at the beginning of the simulation and thereafterwhenever any signal in wait statement changes; • There must be a wait statement to prevent an infinite loop. NO_LIST:process{constant_declarations} {var_declarations}begin{sequential_statements}wait on S1, S2end processNO_LIST; wait on S1, S2 Structured Logic Design with VHDL

35. equal Basic Features of VHDL • Concurrent Statements • Concurrent Assert Statement If BOOL_EXPR is false thenMessage_string is written to the output device. LABEL:assertBOOL_EXPR report“Message_string” severitySEVERITY_LEVEL; LABEL: process (A, B, C) begin assert (A or B) = C report ”...” severity WARNING; end process LABEL; LABEL: assert (A or B)=Creport “C is NOT equal to (A or B)”severity WARNING; Structured Logic Design with VHDL

36. equal Basic Features of VHDL • Concurrent Statements • Concurrent Signal Assignment Statement • Executed: • once at the beginning of the simulation; • at any time any right side signal experiences an event. LABEL: C <= A or B; LABEL: process (A, B) begin C <= A or B; end process LABEL; Structured Logic Design with VHDL

37. Basic Features of VHDL • Concurrent Statements • Concurrent Signal Assignment Statement can be conditional. • Executed: • once at the beginning of the simulation; • when any signal in any WAVFRM or any signal in any COND experiences an event. LABEL:SIGNAL_NAME<=[transport] WAVFRM1whenCOND1else WAVFRM2whenCOND2else ... WAVFRMnwhenCONDnelse WAVFRMq; L1: S <= A or B when XX=1 else A and B when XX=2 else A xor B; Structured Logic Design with VHDL

38. Basic Features of VHDL • Functions can be declared by specifying: • the name of the function; • the input parameters (if any); • the type of the returned value; • any declarations required by the function itself; • an algorithm for the computation of the returned value. Structured Logic Design with VHDL

39. Basic Features of VHDL begin process (START,SYNC) variable CNT: INTEGER :=0; begin if START’EVENT and START=‘1’ then CNT := 2**N-1; end if; PGOUT <= INT_TO_BIN (CNT,N) after PER; if CNT /= -1 and START = ‘1’ then SYNC <= not SYNC after PER; CNT := CNT-1; end if; end process; end ALG; entity PULSE_GEN is generic (N: INTEGER; PER: TIME); port (START: in BIT; PGOUT: out BIT_VECTOR(N-1 downto 0); SYNC: inout BIT); end PULSE_GEN; architecture ALG of PULSE_GEN is function INT_TO_BIN (INPUT: INTEGER; N: POSITIVE) return BIT_VECTOR is variable FOUT: BIT_VECTOR(0 to N-1); variable TEMP_A: INTEGER:=0; variable TEMP_B: INTEGER:=0; begin TEMP_A:= INPUT; for I in N-1 downto 0 loop TEMP_B:= TEMP_A/(2**I); TEMP_A:= TEMP_A rem (2**I); if (TEMP_B = 1) then FOUT(N-1-I) := ‘1’; else FOUT(N-1-I) := ‘0’; end if; end loop; return FOUT; end INT_TO_BIN; Function to convert an INTEGER type to type BIT_VECTOR (fig. 3.25) Structured Logic Design with VHDL

40. Basic Features of VHDL • Procedures can be declared by specifying: • the name of the procedure; • the input and output parameters; • any declarations required by the procedure itself; • an algorithm. Structured Logic Design with VHDL

41. Basic Features of VHDL procedure ADD (A,B: in BIT_VECTOR; CIN: in BIT; SUM: out BIT_VECTOR; COUT: out BIT) is variable SUMV,AV,BV: BIT_VECTOR (A’LENGTH-1 downto 0); variable CARRY: BIT; begin AV := A; BV := B; CARRY := CIN; for I in 0 to SUMV’HIGH loop SUMV(I) := AV(I) xor BV(I) xor CARRY; CARRY := (AV(I) and BV(I)) or (AV(I) and CARRY) or (BV(I) and CARRY); end loop; COUT := CARRY; SUM := SUMV; end ADD; Procedure to add entities of type BIT_VECTOR (fig. 3.26) Structured Logic Design with VHDL

42. Basic Features of VHDL • Subprogram Usage Rules • For procedures: • modes for parameters : in, out, inout ; • object classes for parameters : constant, variable, signal ; • if the mode is in and no object class is specified, constant is assumed; • if the mode is inout or out and if no object class is specified, variable is assumed. Structured Logic Design with VHDL

43. Basic Features of VHDL • Subprogram Usage Rules • For functions: • the only allowable mode for parameters is in ; • the only allowable object classes are constant or signal ; • if the object class is not specified, constant is assumed. Structured Logic Design with VHDL

44. Basic Features of VHDL • Packages • Use them to hold frequently used declarations; • VHDL defines a STANDARD package; • Visible by referring to the package name; • Package body is not required if a package contains no subprograms; • Access to the package is given by the use clause. Structured Logic Design with VHDL

45. Basic Features of VHDL • Packages • Definition of a package: package HANDY is subtype BITVECT3 is BIT_VECTOR(0 to 2); function MAJ3 (X: BIT) return BIT;end HANDY; • Entity LOGSYS “sees” all the declarations from HANDY package: use work.HANDY.all;entity LOGSYS is port (X: in BITVECT3);end LOGSYS; Structured Logic Design with VHDL

46. Basic Features of VHDL • Visibility • Region: A logical continuous portion of a text. • Declaration region: A region in which a name can be used to unambiguously refer to a declared entity. • Once an entity has been declared in the declaration region, its name is visible to the end of that region. • Two types of visibility: • directly, within the region where entity is declared; • by selection, through use and library clauses. Structured Logic Design with VHDL

47. Basic Features of VHDL • Libraries • When VHDL models are analyzed with no errors, the result is stored in a library. • Libraries allow the existing VHDL models to be used in future VHDL descriptions • Two types of libraries: • work library, where current analysis results are stored • resource libraries, referenced during analysis and simulation but cannot be written into Structured Logic Design with VHDL

48. Basic Features of VHDL • Libraries • contain primary and secondary units. • Primary units are: • entity; • package; • configuration declarations. • Secondary units are: • architectures; • package bodies. • they have logical and physical names. • Logical name is: • used in VHDL description; • portable. • Physical name is: • used by the host OS to refer to the library; • -system dependent. Structured Logic Design with VHDL

49. VHDL Structural Model model pointers library models Design Library Basic Features of VHDL • Configurations • VHDL structural architectures are developed by specifying the interconnect between component models that are first declared and then instantiated; • Each instantiated component must be bound to a component model if it is to be simulated. Configuration specification statement: forINSTANTIATED_COMPONENT useLIBRARY_COMPONENT; (fig. 3.29) Structured Logic Design with VHDL

50. entity TWO_CONSECUTIVE is port (CLK,R,X: in BIT;Z: out BIT); end TWO_CONSECUTIVE; use work.all; architecture STRUCTURAL of TWO_CONSECUTIVE is signal Y0,Y1,A0,A1: BIT:=‘0’; signal NY0,NX: BIT:=‘1’; component EDGE_TRIGGERED_D port (CLK,D,NCLR: in BIT;Q,QN: out BIT); end component; for all: EDGE_TRIGGERED_D use entity EDGE_TRIG_D (BEHAVIOR); component INVG port (I: in BIT; O: out BIT); end component; for all: INVG use entity INV (BEHAVIOR); component AND3G port (I1,I2,I3: in BIT;O: out BIT); end component; for all: AND3G use entity AND3(BEHAVIOR); component OR2G port (i1,I2: in BIT;O: out BIT); end component; for all: OR2G use entity (OR2(BEHAVIOR): begin C1: EDGE_TRIGGERED_D port map (CLK,X,R,Y0,NY0); C2: EDGE_TRIGGERED_D port map(CLK,ONE,R,Y1,open); C3: INVG port map (X,NX); C4: AND3G port map (X,Y0,Y1,A0); C5: AND3G port map (NY0,Y1,NX,A1); C6: OR2G port map (A0,A1,Z); end STRUCTURAL; Basic Features of VHDL Configuration specification for entity TWO_CONSECUTIVE (fig. 3.30) Structured Logic Design with VHDL