Belle-II bKLM Readout System Concepts, &c.

1. Belle-II bKLM Readout System Concepts, &c. W. Jacobs, G. Visser, A. Vossen Indiana University CEEM 7/15/2011

2. by Yusa-san (with some added info here) 16 “octants” 16 crates 1356 ch/crate 15 FEE boards/crate 2 cables/board 23 cables/crate fully utilized 7 cables/crate only 36 ch utilized current KLM Barrel : 21696 strips Endcap : 16128 strips Total : 37984 strips New readout: The organization is good, maintain same! Reuse all cables! 1 FEE board ↔ 1 superlayer ↔ 96 ch

3. Signals Z0= 50 Ω microstrip Z0= 113 Ω twisted pair 50 Ω Length 5.1 – 6.1 m 50 Ω Existing scheme (above) – NOTE ground at both ends of cable. Voltage/noise externally imposed between these grounds will simply add to signal+threshold input to comparator. Not great. Preferred scheme would break this ground connection at FEE boards: Z0= 50 Ω microstrip Z0= 113 Ω twisted pair 50 Ω Length 5.1 – 6.1 m 50 Ω

4. Frontend circuit MAX9010 • Optionally can tie the “ground” side of inputs • To ground • Simply together • To ground through capacitor • Or just leave them untied here (probably best)

5. TDC (FEE Board) 48 channels per FPGA, 2 FPGA (XC6SLX..) per board mask 250 MHz clock kill good hit now discriminator S Q R D Q D Q D Q counter W FIFO to backplane / concentrator augment w/ chan number on output common to 48 ch • readout logic will ensure that all good hits are sent to backplane output within 1 μs • 8 bits = 1 μs rollover is OK • augmented with coarse bits on receiving side • ?? SIMPLY DROP tardy hits (which would be due to excessive occupancy) ??

6. Concentrator / Crate Master Board Input from 13 (15??) FEE Boards Maximum 13×25/3 = 108 MHz hit rate = 433 MB/s output data rate Typical expect a few kHz, buffers will never be full 250 MHz clock (FPGA internal) 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO FEE 0 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO 29 hit processing TX FIFO 32 B2link TX to trigger 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO 1024×5 → 256×20 FIFO 1280×5 → 256×25 FIFO FEE 12 backplane 13 independent datapaths use 65 bussed/terminated lines 5 bits @ 25 MHz 3 words per hit from FEE (7 bit channel & 8 bit fine time) augment with 10 bit coarse timestamp augment each FIFO output data w/ FEE # circular buffer triggered hit processing TX FIFO 32 B2link TX to DAQ • hit processing latency into trigger TX FIFO: • 5-6 250 MHz cycles in FEE/TDC • 3 (+2 pipeline) backplane clock cycles = 200 ns • 3-4 250MHz pipeline cycles in frontend FIFO • 1 read cycle + 1 pipeline • 0 or more processing cycles... • 1-2 250MHz pipeline cycles in TX FIFO • → overall about 260 ns • of course, more if waiting on resources busy with prior hit B2 trigger OR?? only one link, send all hits, ignore trigger (or send message on link?), no selection of “triggered” hits in window ??

7. Backplane • Use the backplane entirely synchronously, w/ 25 MHz (or more) clock on SYSCLK • FEE boards multiply it to 250 MHz for fine timestamp (TDC reference clock) • Synchronous reset is pulse width encoded onto SYSCLK, used to align fine timestamps across system. Belle II trigger is not used on FEE boards, only on controller board (if at all). • The incoming reference clock from Belle-II timing distribution is divided down on the controller board to feed SYSCLK. • A few lines (DTACK, AS, SYSFAIL, BERR, SYSRESET) are reserved for slow controls, details TBD. Also SERA/B are reserved (termination status tbd on these backplanes). • Main datapath is 65 bits wide, BDM (“bit division multiplexed”) across 13 (or fewer) FEE boards: D(16), A(24), AM(6), IRQ(7), BBSY, BCLR, ACFAIL, DS(2), WRITE, IACK, LWORD, BR(4). Each FEE board has an independent path to controller board, no wait on backplane resources, low latency. • Hits mostly will consist of tracks running through several layers, so several FEE boards, these will proceed independently through the backplane without waiting on each other. This is important. • FEE boards have driver only on these data lines, probably use open-drain driver through Schottky diode to backplane, so non-driving board will present very minimal load (e.g. 2 pF vs. 11 pF). Whatever the scheme, prototyping will be required of course, to achieve maximum speed in final design.

8. Summary of principal specifications • Sensitivity: <4 mV • Time walk (5 to 40 mV overdrive): 8 ns is expected (from stated pulse shape) • Threshold: 0 – 100 mV, 7 bit DAC per channel • TDC bin: 4 ns • Latency to process single hit (to trigger link output): <300 ns • Latency to process 2 hits per layer, all layers, to trigger link output: <TBD • Input connections: pinout, connectors, general layout in crate to match old system • Test pulser: Per channel enable, common level control and trigger • Channels per connector: 48 • Connectors per FEE board: 2 • FEE boards per crate: 13 (15??) • Concentrator boards per crate: 1 • DAQ fibers per concentrator: 0 or 1 ?? • Trigger fibers per concentrator: 1 • Trig/clock input per concentrator: 1 • Crates per system: 16 • FEE boards to build: 13×16+20% = 250 • Concentrator boards to build: 16+30% = 21 or, how do we want to set this spec?