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Testing and DFT tools

( Installed in our PLD Lab ). TURBO TESTER. Testing and DFT tools. Maksim Jenihhin. IXX9500 Doktoriseminar. DFT Package tools. DFT Advisor – insert internal scan circuitry BSD Architect – insert boundary scan circuitry Fast Scan – quick full-scan ATPG and fault simulator

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Testing and DFT tools

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  1. ( Installed in our PLD Lab ) TURBO TESTER Testing and DFT tools Maksim Jenihhin • IXX9500 Doktoriseminar

  2. DFT Package tools • DFTAdvisor–insert internal scan circuitry • BSDArchitect – insert boundary scan circuitry • FastScan – quick full-scan ATPG and fault simulator • FlexTest – sequential ATPG and fault simulator • LBISTArchitect – insert logic BIST circuitry • MBISTArchitect – insert memory BIST circuitry • Embedded Deterministic Test (EDT) and TestKompress - generate and compress deterministic test patterns server:/home/user>cat .cshrc … setenv MENTOR setenv MENTOR_64 …

  3. Design Flow DF

  4. Design ATPG Library Tools: DFTAdvisor FlexTest LBISTArchitect etc. ATPG library Levels: RTL Gate ATPG library is NOT required if the design netlist fully defines all the primitives. (It can occur only in Verilog and TDL formats.) Formats: EDIF VHDL Verilog Genie TDL Model Where to get one? • 1. Use one preinstalled for Mentor Graphics training examples. • To locate it use find command. • 2. Use class.atpglib compatible with Turbo Tester class.lib (Synopsys) • www.pld.ttu.ee/~maksim/mg/class.atpglib • 3. Create your own for your particular library: • a. Manually • b. Use LibComp to translate it from Verilog > find /cad/m_04/ -name atpglib -print ... /cad/m_04/dft/shared/pkgs/testkompress.ss5/systest_data/atpglib

  5. MG DFT Documentation • Local /cad/m_04/dft/shared/pdfdocs • Mentor Graphics SUPPORTNET (requires free registration) http://www.mentor.com/supportnet/ • External storage of Mentor Graphics Design-for-Test ’99 documentation: http://www.fm.vslib.cz/~kes/bs/mg/mg.html

  6. Synopsys TetraMAX Offers a choice of ATPG modes: Basic-Scan ATPG, an efficient combinational-only mode for full-scan designs Fast-Sequential ATPG for limited support of partial-scan designs Full-Sequential ATPG for maximum test coverage in partial-scan designs It is integrated with Synopsys’ DFT Compiler.

  7. Hazard Analysis Data Multivalued Simulation Test Generation Test Set Specifi-cation Design Defect Library Fault Simulation BIST Simulation Test Set Optimization Faulty Area Design Error Diagnosis Fault Table TURBO TESTER Environment Algorithms: Deterministic Random Genetic Circuits: Combinational Sequential Formats: EDIF AGM Levels: Gate RTL Fault models: Stuck-at faults Physical defects Methods: BILBO CSTP Hybrid

  8. TT Development Team Prof. Raimund Ubar Jaan Raik Elmet Orasson Artur Jutman Gert Jervan Margit Aarna Eero Ivask Sergei Devadze Vladislav Vislogubov Maksim Jenihhin Department of Computer Engineering Official website: http://www.pld.ttu.ee/TT

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