WP-JP-S Electro/optic switching architectures First Review Meeting Brussels, 23-24 May 2007

1. WP-JP-S Electro/optic switching architecturesFirst Review MeetingBrussels, 23-24 May 2007 WP Leader: A.Stavdas Speaker: Christinna (Tanya) Politi University of Peloponnese

2. Overview • JP on Electro/optic switching architectures • Led by University of Peloponnese • Estimated 58 Person months effort • Starts on Month 2 • End on Month 24

3. Objectives • To assess the merit of all-optical, optoelectronic and electronic switching subsystems and technologies and the synergy between the different technologies for an overall cost-effective solution • Study hybrid electro-optical switching architectures. Where appropriate, the corresponding multi-layer node could be comprised by “optically transparent” and “opaque” layers • Technologies and sub-systems for low cost O-E conversion exploiting fixed-receiver-tunable-transmitter, fixed-transmitter-tunable-receiver schemes • Control complexity assessment of hybrid optoelectronic solutions and optical interconnect solutions • Migration scenarios from purely electronic switching to optoelectronic towards all-optical. • CAPEX studies with emphasis given on power consumption considerations

4. Involved Partners • PoliTO • DEIS-UniBO • PoliMI • UoA • UoPelop • UniVi (collab. Inst.)

5. Advisory Board • Andrea Bianco (PoliTo) • Achille Pattavina (PoliMi) • Carla Raffaelli (DEIS) • Dimitris Syvridis (UoA)

6. Meetings and Workshops • 1st JPS Conference Call • Host: UoPelop • Location: Monday 4-Dec-06, 12:00 CET • Type: Finalisation of JPS list of actions, definition of DJPS.1 contents • 2nd JPS Meeting • Host: UPC • Time: Monday 26-Feb-07 14:30-18:00 • Location: Room C6-220 • Type: Review of JPS activities, plan for DJPS.2

7. JP-S Organization • Vertical work organization focusing on the quantitative evaluation of the identified research topics • Collaboration sought to achieve unity of contributions • Main focus: evaluation of hybrid opto-electonic switch architectures • Photonic components as switch elements & fabrics • Migration scenarios from purely electronic switching to optoelectronic towards all-optical • Switch control complexity assessment vs. network performance (loss, delay, utilization)

8. Role & Contribution of Partners (1) • UoP • Network and hybrid node architectures for efficient traffic control • Performance of a Hybrid T-S 1:N shared node in isolation • DEIS-UNIBO • Hybrid node architectures for increased network performance • Evaluation of alternative full 3r T-W-S switch node architectures • POLITO • Evaluation of optical switching fabric architectures • Synchronous vs. asynchronous operation

9. Role & Contribution of Partners (2) • POLIMI • Evaluation of optical switching fabric architectures • Evaluation of optical switching fabric architectures • UVI • Evaluation of efficient switch scheduling implementations • Decoupled iSLIP: D-iSLIP • UoA • Optimized (electrical power consumption & cost effectiveness) switching techniques • Performance evaluation of switching components based on MR resonators

10. Two directions for the MNs • Full O-E conversion in every node including 3R regeneration and buffering capability of the entire incoming traffic. • Hybrid node. Only a fraction of the incoming traffic is O-E converted and possibly buffered. Also a transparent L2 electronic switch can be deployed. • The two approaches leading to networks with entirely different performance characteristics

11. Queue Manager Scheduler 1 NxM VOQ l1 Queue Manager Scheduler Rx Tx Tx Rx lM Full 3R: T-S configuration Drop/Transit OXC O/E - 3R buffering outbound Class-O

12. Drop/Transit OXC O/E - 3R buffering Wavelength conversion outbound Full 3R: T-S-W configuration Class-IIA Class-IIB Partial Class-I

13. Queue Manager Scheduler Rx Tx Queue Manager Scheduler TTx Rx M x M AWG router lk An O/E subsystem: The T-W Module

14. Hybrid: T-S Drop/Transit OXC 3R buffer Transparent Electr. switch outbound O/E + L2 switch

15. Hybrid: T-S 1+1 configuration (N+1):1 1:(N+1) 3R + buf. 3R +buf. L2 transparent Slot DXC 3R + buf. 3R +buf. 3R + buf. 3R +buf. • For every incoming fiber, there is a dedicated drop port at the input • However, only K out of M wavelengths can be 3R • Equally, the transparent electronic switch handle only a fraction of the incoming capacity outbound

16. Research Considerations • Adopting either the “telecom” or the “router” approach leading to networks with entirely different properties • Equally, the different node configurations are closely related to the underneath network type. • Example: Physical layer performance. With full O-E regeneration, a large number of nodes can be cascaded. Cost + power consumption is an issue

17. UoP

18. First year objectives • Architectures providing a near optimal trade-off between • Dynamic resource allocation • Efficient bandwidth utilization • Switch implementation complexity and cost • Latency & application level performance • Controlling loss and latency in dynamically reconfigurable architectures is a requirement towards efficient network resource utilization

19. D.E.I.S

20. l1  module 0 0 lM Bit-Synchronisation and buffering card Bit-Synchronisation and buffering card Bit-Synchronisation and buffering card Bit-Synchronisation and buffering card N:1 N:1 1:N 1:N N-1 l1 N-1 1:N EDFA TWC ON/OFF gating 1:N coupler lM Alternative Full 3R T-W-S

21. Scope • Set up a simulation tool to evaluate performance in the presence of electronic buffers • Synchronous • Packet loss • Queueing policies • Service differentiation • Evaluation of joint exploitation of different contention resolution domains • Time, wavelength, space

22. Poli. Mi

23. POLIMI proposal • PoliMI will be focusing on the following issues: • Realization of the M-to-K wavelength selector (O-E converting stage) by different “mixing” of electronic and all-optical sub-stages • Loss-behaviour comparison of the different O-E converting stage implementations • Optical-switching fabric: investigation of AWG-based alternatives to replace the B&S Class-O block

24. Poli. To

25. Framework of the planned work • Focus on optical switching fabric • Asynchronous architectures • Variable length packets • Asynchronous arrivals • No packet or slot alignment needed • Buffering • No buffering • Electronics buffering at inputs • Performance analysis • Throughput saturation model and simulation • IQ switch with large number of ports • Infinite queue size • Throughput vs packet lenght distribution (coefficient of variation) • CV=0 behaves as synchronous switching (58% throughput) • When CV=1 and no buffer available, 50% throughput instead of 63%

26. UVI

27. Electro-Optical Architecture • EOXC electronic sub-system design limitations: • Hardware decoupling is beneficial for practical implementations • Highly demanding performance requirements

28. Not feasible Which Scheduler? • Maximal Size Matching: Parallel Hierarchical Matching (PHM): • Delay: Low delay. • Stability: Uniform and i.i.d. traffic.  Scalability: O(N2) on-line complexity. • Number of iterations: O(log2N). • Load Balanced Birkhoff-von Neumann:  Scalability: O(1) on-line complexity.  Number of iterations: O(1).  Stability: 100% under weakly mixing traffic.  Delay: High delay. Decoupling PHM: • Trade-off between LB-BvN and PHM properties.

29. UoA

30. Optimizied switching components • MR resonators as photonic switching components • Performance and power consumption trade-offs

31. JP Budget Allocation Criteria • Contributions to deliverables • Participation in meetings • Preparation of joint papers • The first two above are mandatory. • Initial estimation for the reserved WP budget based on the assumption of equal participation. • Partners have agreed to these rules. • In case the expected contributions are not received, adjustments to the budget allocation may be made

32. Joint Papers • C. Raffaelli (DEIS-UNIBO), M. Savi (DEIS-UNIBO), A. Stavdas (UoPelop), Sharing Wavelength Converters in Multistage Optical Packet Switches, Proceedings HPSR 2006, Poznan (Polanda), June 2006. • D. Careglio, G. Muretto, C. Raffaelli(DEIS-UNIBO), J. Sole-Pareta (UPC), E. Vignes, Quality of service in a Multi-Fiber Optical Packet Switch, Photonics in Switching 2006, Greece, October 2006. • C. Raffaelli (DEIS-UNIBO), M. Savi (DEIS-UNIBO), A. Stavdas (UoPelop), Performance of Scheduling Algorithms in Multi-stage Optical Packet Switches with Sparse Wavelength Converters, Proceedings of IEEE GLOBECOM 2006, San Francisco, U.S.A., November 2006. • R. Zanzottera (POLIMI), C. Matrakidis (UoPelop), A. Stavdas (UoPelop), S. Sygletos, A. Pattavina (POLIMI), Design of OXC architectures based on arrayed waveguide gratings: topological properties and physical performance, IEEE Conferecne on High Performance Switching and Routing, pp. 257-263, Poznan, June 2006. • C. Raffaelli (DEIS-UNIBO), M. Savi (DEIS-UNIBO), N. Akar (BILKENT), E. Karasan (BILKENT), Packet Loss Analysis of Synchronous Buffer-less Optical Switch with Shared limited Range Wavelength Converters, Workshop on High Performance Switching and Routing (HPSR2007), May 2007.

33. Plan for Second Year

34. Scientific and Technical Impact

35. Final Comments