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TECHNOLOGY TRENDS

TECHNOLOGY TRENDS. TOWARDS 10GT. 10 GT in 2015. 1 GT in 2010. Multi-core. Quadcore. Dual core. 64-bit. 32 bit. 16 bit. 8-bit. FASTER MEMORY/PROCESSOR DATA EXCHANGES. Data Rate per pin (Gb/s). We are Here. 100 Gb/s. Mobile Memory. Data exchange between processor and memories

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TECHNOLOGY TRENDS

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  1. TECHNOLOGY TRENDS

  2. TOWARDS 10GT 10 GT in 2015 1 GT in 2010 Multi-core Quadcore Dual core 64-bit 32 bit 16 bit 8-bit

  3. FASTER MEMORY/PROCESSOR DATA EXCHANGES Data Rate per pin (Gb/s) We are Here 100 Gb/s Mobile Memory Data exchange between processor and memories • Needs for increased data rate 3D WideIO2 WideIO DDR4: 250ps 2D LPDDR4 10 Gb/s DDR5 LPDDR3 DDR4 LPDDR2 DDR3 Laptop Memory DDR2 LPDDR1 1 Gb/s 2010 2012 2014 2016 2018 2020

  4. Core supply SUPPLY VOLTAGE SCALE DOWN Supply (V) 7-nm technology 5.0 0.65 V inside, 1.0 V outside 3.3 I/O supply 2.5 1.8 1.2 1.0 90n 32n 130n 45n 20n 0.35µ 0.18µ 65n 7n 14n 10n Technology node

  5. TERA-BIT STORAGE We are Here Technology • 2.5D high bandwidth and high density DRAM with TSV and Si Interposer • 1 tera-bit/cm2 achieved 5 years ahead from roadmaps

  6. SCALE DOWN BENEFITS • Smaller • Faster • Less power consumption • Cheaper (if youfabricate millions) 65nm 28nm 14nm Power -50% -80% 28nm 65nm 14nm

  7. SCALE DOWN BENEFITS Maximum die size • 8 coresinstead of 1 using the samespace • 3 times faster • 10 times less power consumption One Core One core AMD dual core 65nm Intel Octa core 22nm

  8. TECHNOLOGY INNOVATION & COST • Strain, eSiGe, • High-K, low-K dielectric, Airgap • Metal gate • FinFET • Double, quad patterning

  9. TECHNOLOGY TRENDS TOWARDS BILLION $ FAB

  10. 10-NM CHIPS • Samsung Exynos 8895 in 10-nm • IBM, GlobalFoundries, Samsung, SUNY first 7-nm testchip • Samsung Snapdragon 635 in 10-nm

  11. TECHNOLOGY INNOVATION & COST • Less and lesscompanies in the 14-nm market Keynote_AjitManocha_GLOBALFOUNDRIES

  12. TECHNOLOGY INNOVATION & COST

  13. ROADMAP ACCORDING TO TSMC http://www.tsmc.com/english/dedicatedFoundry/technology/future_rd.htm

  14. GOING 3D – Package on Package MEM to SoC (TMV) Upper MEM PCB PCB Bottom SoC MEM to PCB (TMV) SoC to PCB E. Sicard, EMC performance analysis of a Processor/Memory System using PCB and Package-On-Package, EMC Compo 2015 Edinburgh

  15. GOING 3D – Stacked Dies Through Silicon Via (TSV) Possible 3rd die Processor die Thinned memory die 10 µm Direct bond interconnect (DBI) THERE IS PLENTY OF SPACE ON THE TOP • 3D technology uses stacked dies, through-silicon-vias • Enables 10-20 Gb/s/pin at 1.0V • Samsung 3D (Galaxy 6) vs PoP (Galaxy 5) : 30% faster 20% less power Less heat Upper die Multicore 350 µm thickness Bottom die Package leadframe(GND) http://www.youtube.com/watch?v=Rw9fpsigCfk

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