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POSSIBLE OPTIONS TO TEST THE LAST DRS VERSION (IV) AT DREAM

POSSIBLE OPTIONS TO TEST THE LAST DRS VERSION (IV) AT DREAM. F.Scuri for the DREAM Pisa group. The DRS version IV chip The CAEN project of a VME card based on DRS-IV The PSI DRS-IV evaluation board Some possible scenarios for the next Dream test beam(s).

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POSSIBLE OPTIONS TO TEST THE LAST DRS VERSION (IV) AT DREAM

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  1. POSSIBLE OPTIONS TO TEST THE LAST DRS VERSION (IV) AT DREAM F.Scuri for the DREAM Pisa group • The DRS version IV chip • The CAEN project of a VME card based on DRS-IV • The PSI DRS-IV evaluation board • Some possible scenarios for the next Dream test beam(s) DREAM Collaboration Meeting, Rome, March 16-17, 2009 F. Scuri - Possible options...

  2. DRS-IV main characteristics (reference manual) Input capacitance: 15 pF (between IN+ and GND, Domino wave stopped) Equiv. impedance: 6.3 KW/fs[GHz] Bandwidth (-3dB) = 950 MHz Sampling speed : [0.01-5] Gsps Readout speed: [10-40] MHz (33 MHz optimal value) ROI readout mode implemented !  Readout time for n cells: 30x(n+1) ns Temperature drift: Offset error: 75 mV/oC Gain error : 25 ppm/oC Mesured between 25 and 50 oC:what happens below 25 oC (as in the counting room) and at high activation rate (as at the test beam)? Need to be measured ! F. Scuri - Possible options...

  3. DRS-IV linearity characteristics (reference manual) F. Scuri - Possible options...

  4. Other DRS-IV relevant characteristics (reference manual) This is the only DRS-IV “official” plot on temperature effects (DSPEED = Domino wave pilot frequency) Unstabilized jitter: ~200ps (at 5 Gsps) ~200 psec R. Paoletti, N. Turini, R. Pegna, MAGIC collaboration F. Scuri - Possible options...

  5. Typical configuration of a DAQ system based on DRS-IV To external CTL/Data bus (VME, USB, Optical link,…) External trigger to start the cell voltage read-out and conversion cycle F. Scuri - Possible options...

  6. Shell we test a DRS-IV based system in DREAM? No published measurements are yet available for DRS-IV on: - calibration stability versus temperature; - cross-talk level between channels in pulsed mode; - sampling capacitor full refresh cycle as a function of sampling and trigger frequencies (A new “Clear” circuit designed for capacitor refresh –S.Ritt, FNAL08) Only oral communication between people working with previous DRS versions (Magic, MEG, Dream….)  need to check whether the relevant improvements claimed for DRS-IV are suitable for DREAM or not. Two possible scenarios for the next DREAM test beam (July 15-30, 2009): a) A prototype of a 16 or 32 analog-in channel with DRS-IV under design at CAEN will be available in time (very unlikely) b) As back-up solution, based on a test a stand-alone DRS-IV evaluation board; one unit ordered to PSI from Pisa (only 4 analog in, only USB interface for read-out, delivered by the end of March…) F. Scuri - Possible options...

  7. The CAEN project for a VME card with DRS-IV chips CAEN and DRC-Pisa agreed to co-operate in testing a DRS-IV VME board since beginning of 2009; - CAEN people are interested to test their prototype on a real detector; - Dream needs to understand a.s.a.p. whether all limitations encountered in the 2008 test beam data analysis with DRS-II could be overcome with the new chip or not. Under Dream Collaboration approval, CAEN could be invited to test their prototype at next test beam campaign – Problem is the time schedule…… ….CAEN effort is driven by the perspectives of applicability for next detector generation with large number of read-out channels at future colliders. The following slides are a summary of my personal understanding of the CAEN project main characteristics….. F. Scuri - Possible options...

  8. CAEN will exploit an existing motherboard as for V1740…. 32 bit local bus 12 bit – 200 Ms/s (can be fed to analog inputs for calibration) DAC VME interface • FRONT PANEL • 16 progr. I/O • TRIG_IN • TRIG_OUT • - SYNC_IN FPGA 1.25 Gb/s 70 MB/s (120 MB/s 2ESST) Can be used to generate a busy signal and the event nr. REF. CLK PLL 16/32-channel *)65 MS/s-12bit digitizer “boosted” by DRS4 chip to 5 GHz PCI/PCIe Optical link interface Phase adjust OSC For daisy chained unit read-out purposes CLK OUT CLK IN *) With DRS at 5Gs/s 16 input chs guaranteed, for 32 chs. cross-talk could be an issue…. F. Scuri - Possible options...

  9. FPGA FPGA FPGA FPGA ADC ADC ADC ADC MEM MEM MEM MEM ADC ADC ADC ADC The motherboard – 4 daughterboard (mezzanine) scheme daughterboards motherboard FPGA LOCAL BUS Analog inputs F. Scuri - Possible options...

  10. The single daughterboard (mezzanine) lay-out TRIGGER FPGA LOCAL BUS CTL 12 bit / 65 MS/s Octal ADC DRS IV 8 8 ANALOG INPUT AMPL X 8 SRAM 4MB 30 MHz CLK Calibration constants Event size (8 chs) (no ROI option used): 8 x 1024 x 12 = 100 Kb Throughput (1 KHz trigger freq.) : 100 Mb/s  32 chs.:  400 Mb/s  50 MB/s max. 200 MB/s bandwidth F. Scuri - Possible options...

  11. Possible scenarios if a prototype will be ready for next Dream test beam Dream calorimeter tower geometry: 19 scintillation +19 Cherenkov analog inputs Leakage counters • Analog signals to be converted: • trigger (to define the ROI w.r.t. • the asynchronous Domino wave) • up to 9 leakage counters • 2 x19 calorimeter towers Total: 48 analog inputs • 2 x 32 ch. VME units (3 x 16 ch.) will fit the request Even a 16 ch. prototype would be useful: Trigger : 1 ch. Cherenkov: tower 1 + S (inner and outer ring) : 2 chs. Scintillator: towers 1 to 7 + S (outer radius) : 8 chs. Leakage: S (up count.) + S (down count.) + S (left count.) + S (right count.) : 4 chs. Total :15 chs. F. Scuri - Possible options...

  12. Finalizing the collaboration with CAEN • CAEN project for a 16/32 chs. VME digitizer with DRS-IV seems to fit • very well with the Dream needs for time profile analysis of the hadronic • calorimeter; • CAEN developers are interested in testing their cards on a “real” detector • like Dream and, eventually, in assisting us during data taking at the test beam; • however…. • CAEN time schedule (first prototypes by 2009 fall) doesn’t fit with the • Dream 2009 scheduled T.B. (July 15-30); very low probability that they will • be ready for the scheduled T.B. •  is there any chance to repeat/postpone a data taking week with Dream • just before year 2009 ends? •  If not, there will be future activities in 2010 of the Dream Collaboration • (not necessary with the present detector) to keep alive motivation to • collaborate with CAEN on fast digitizers based on DRS chips ? F. Scuri - Possible options...

  13. The back-up solution: the PSI DRS-IV evaluation board One unit ordered (840 Euro, taxes included), should be by available for tests in Pisa by the end of March… F. Scuri - Possible options...

  14. PSI DRS-IV evaluation board main characteristics A stand-alone compact board including: *) By channel cascading, 8 DRS inputs are paired to obtain four channels with a 2048 sampling cells array *)Self-triggering on a programmed level of any of the 4 input channels F. Scuri - Possible options...

  15. Temperature sensor A peculiar and very important feature of the PSI evaluation board is that there is a temperature sensor of the board, placed just aside the DRS-IV chip FPGA firmware is designed to read temperature with the “info” command. Temperature sensor F. Scuri - Possible options...

  16. This is your full DAQ system! ….well, not exactly….. F. Scuri - Possible options...

  17. Minimal layout in ”stand-alone” mode S Evaluation board HOST COMPUTER USB-II S Trigger IN Level Adapter Dream Trigger logic Open question: how to synchronize with Dream DAQ? Need at least a DRS busy signal and an event number generator … waiting to discuss with S.Ritt CLOCK (trigger for pedestal evts.) In case will could have 4 evaluation boards, read with a PCI high speed (480 Mb/s) 4-USB port driver, we could repeat the CAEN 16 input scheme ….. F. Scuri - Possible options...

  18. Conclusions • The analysis of data taken with DRS-II at 2008 Dream test beam is still • in progress and far to be completed; however, some preliminary conclusion • can already be done: • a) DRS showed its potentiality in time profile analysis of PM signals • (neutron fraction measurement) • b) many limits have been found/confirmed for the version “II”: • - temperature drift effects; • - strong non linearity requiring frequent and not so simple calibrations • - not complete cell refresh on “reset” resulting in baseline jitter; • - not optimized line coupling of capacitor to ADC resulting in a long • signal decay time. • In the last version (IV) of the DRS chip, many of the limits listed above have • been moderated  need to prove it in particle detector environment. • There are some options to test DRS-IV at next Dream test beam(s) • (CAEN VME prototype, PSI evaluation board) • Question for the Collaboration: should we go on with DRS-IV? F. Scuri - Possible options...

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