A Proposal for Routing-Based Timing-Driven Scan Chain Ordering

1. A Proposal for Routing-Based Timing-Driven Scan Chain Ordering Puneet Gupta1 Andrew B. Kahng1 Stefanus Mantik2 (abk,puneet@ucsd.edu, smantik@cadence.com) 1: UC San Diego 2: Cadence Design Systems Inc.

2. Outline • Introduction and Previous Work • Motivation • Our Contributions • Timing Aware Connection • Experiments • Conclusions

3. SI SI SI Q Q Q FFA FFB FFC PO PI Introduction and Previous Work • Scan chains are commonly used to enhance testability. All flip-flops are chained to form a shift register. • A goal of DFT is to minimize the impact of test circuitry on performance. • Minimizing wirelength overhead of scan is essential.

4. Q Q A B SI SI B’ Q Q A’ SI SI Pin-to-pin distance Q Q A” B” SI SI Introduction and Previous Work • 3 different distance metrics considered for modeling scan chain ordering as TSP • Nature of TSP • Cell-to-cell: Metric, symmetric • Pin-to-pin: Almost symmetric and almost metric • Pin-to-net: Asymmetric and Non-metric • Our [ASPDAC’03] work: Trial routing driven pin-to-net distance metric gives best WL results (upto 80% better than industrial P&R tools) Cell-to-cell distance from FFB to FFA Pin-to-net distance

5. d(Q,SI) Q SI d(Q’,SI) FFB FFA Q’ Routing Aware Scan Chain Ordering (ASPDAC’03) • Incremental routing cost based on existing or anticipated routing. • Considers both Q and Q’ outputs for the minimum wirelength connection. • Driven by global routing or trial detailed routing. Routing tree of Q’

6. Motivation • No timing awareness in previously published literature • Industry design methodologies constrain the FF output pin to be used for scan connection • 60% of scan nets fall into this category in our test cases • Potentially large WL overhead • Unnecessarily constrains synthesis and layout

7. Our Contributions • A method to compute timing driven incremental connection to existing route • A buffer insertion method when timing is not met • We highlight a potential use in scan chain ordering

8. Timing Aware Connection • Divide routing tree into optimization segments. E.g., o1 (begin1 end1) • 1: influenced sink for o1 • 2: uninfluenced sink • Elmore delay model used

9. Optimal Attachment Point • For uninfluenced sink 2 Linear dependence • r(l(root,b21)) * (c(x1+l(SI,v1))+CSI ) Slack1 • xmin = Slack1/ rc(l(root,b21)) – CSI/c - l(SI,v1) • For influenced sink 1Quadratic dependence • r(l(root;b11)+l(begin1;v1) (c(x1+l(SI;v1))+CSI)  Slack2 • Compute xminusing quadratic expression theory • Closed form solution for xmin given in the paper • Compute xmin for all sinks and optimization segments • Smallest xmin  Minimum WL timing-feasible attachment point d(Q,SI)

10. ATSP Optimization • Calculate optimal attachment points for (Q,SI) and ( ,SI) • TSP edge cost = min(d(Q,SI), d ( ,SI) ) • No timing-feasible connection  label cost as a large number M • Solve the ATSP • M cost edges marked for buffer insertion • ScanOpt used as the solver (http://vlsicad.ucsd.edu/GSRC/Bookshelf/Slots/ScanOpt/)

11. Buffer Insertion • Assume fixed buffer sites with given locations • Compute optimal attachment points for every (buffer site, M cost edge in the TSP tour) pair • Cost of assigning a buffer site B to an edge e(ff1,ff2) = WL(ff1,B) + WL(B,ff2) • Solution of the assignment problem  buffered scan chain solution

12. Tour Structure Dissimilarity • Flows • I: Pin-to-pin distances • II: Pin-to-net • III: Timing Driven • Testcases • 1226 scan FFs • A, Aswap, Aexpand have different placements • Dissimilarity = % of different edges in the tour

13. Implementation with Industry Router Fails • Vpin based incremental routing with Cadence Wroute: • Placing vpins on routing grid avoiding other pins • Placing vpins as regions as well as points • Routing from scratch as well as ECO • Pre-routing scan nets as well as routing all nets together • None of the above work • Routing never completes

14. Conclusions • We have given a proposal for • Incremental connection of a pin to a routing tree • Insertion of buffers in case timing is violated • Basis for true timing driven scan chain ordering • Not able to validate the flow due to router not being able to handle vpins properly • Need layout tools that can handle constraint dominated usage contexts