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DARPA/ITO Adaptive Computing Systems PI Meeting San Juan, Puerto Rico October 6-8, 1999

SLAAC S ystems L evel A pplications of A daptive C omputing Delivering ACS Technology to Applications. DARPA/ITO Adaptive Computing Systems PI Meeting San Juan, Puerto Rico October 6-8, 1999 Project Lead: Bob Parker Presented by: Steve Crago Information Sciences Institute. Outline.

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DARPA/ITO Adaptive Computing Systems PI Meeting San Juan, Puerto Rico October 6-8, 1999

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  1. SLAACSystems Level Applications of Adaptive ComputingDelivering ACS Technology to Applications DARPA/ITO Adaptive Computing Systems PI Meeting San Juan, Puerto Rico October 6-8, 1999 Project Lead: Bob Parker Presented by: Steve Crago Information Sciences Institute

  2. Outline • Overview • Hardware Status • “Customer” Applications • Electronic Countermeasures Analysis (ECMA) • Sonar Beamforming

  3. SLAAC Objectives • Define a system-level open, distributed heterogeneous adaptive computing architecture • Design, develop and evolve scalable reference platforms implementing the adaptive systems architecture • Validate the approach by deploying reference platforms in multiple defense application domains • SAR ATR • Sonar Beamforming • ECMA • Others

  4. System Level Applications of Adaptive Computing Utilizing Three Phases of Adaptive Computing Components Large Current Generation FPGAs Rapid Reconfigurable and/or Fine Grain FPGAs Hybrid FPGAs Integrating Multiple Constituent Technologies Gigabit/Sec Networking Modular Adaptive Compute Modules Network Based Runtime Control Software Algorithm Analysis/ CompilationTools Developing Reference Platforms Flight Worthy Deployable System Low Cost Researchers Kit Lab Demo of an ACS implemented SAR ATR algorithm First Generation of Reference Platforms Embedded SAR ATR Demo of ACS HW (Clear, 1Mpixel/s, 6TT) Significant reduction in power, weight, volume, and cost for several challenging DoD embedded Embedded SAR ATR Demo (CC&D, 1Mpixel/s, 6TT) applications Embedded SAR ATR Demo (CC&D, 10Mpixel/s, 6TT) • •Demonstrate500x reduction in system • volume on SAR/ATR ACS challenge • DemonstrateFirst forward looking, 50,000 beam • towed array on ACS sonar challenge ‘97 ‘98 ‘99 ‘00 ‘01 Team Members: USC/ISI (Lead), BYU, UCLA, VT, Sandia National Labs, LANL, LM-GES

  5. SLAAC Affiliates

  6. SLAAC Technologies Hosts Nodes Network Runtime System Hardware - SLAAC, WILDFORCE, WILD-ONE, ... SLAAC Module Generators Application Mapping T72 SLAAC is delivering ACS technology! T72

  7. Technology Integration Design Environments (Adapters, Cameron, Matlab) Runtime Extensions (Debug, Dynamic Reconfiguration) JHDL (CDs available) Debugger Environments (Boardscope) SLAAC New Chips (Virtex, ACS chips) Module Generators (FOA compiler, DEFACTO) I/O (QC-64, Myrinet) JBits ACS technology is targeting SLAAC!

  8. SLAAC Node Architecture • VHDL model available • Model Technologies • Synopsys • JHDL port coming soon… SRAM X1 X2 X0 IF 

  9. SLAAC-1 Board • Simulation Environment • Drivers • Windows NT driver running • Linux driver coming soon… • Runtime system • SLAAC API (http://www.ccm.ece.vt.edu/slaac/) • Synthesis • Synplicity • Synopsys X1 X2 X0 IF 

  10. SLAAC-1 Status • Working hardware! • Transitioned to university labs • Designs running in all FPGAs Order from lcarter@east.isi.edu

  11. SLAAC-2 Board 40 / 40 / X1 X2 X1 X2 72/ 72/ X0 X0 IF IF   PowerPC Bus A PowerPC Bus B • Simulation Environment • Drivers • VxWorks • Runtime system • SLAAC API • Synthesis • Synplicity • Synopsys

  12. SLAAC-2 Status • Working hardware! • Delivered to Lockheed Martin-GES • Designs running in all FPGAs Order from lcarter@east.isi.edu

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