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22444 - Computer Architecture & Organization (1). Pipelining. Pipelining. Applied to sequential steps to speed up operation Example : Compute R i = A i B i + C i for i=1, 2, … n. Perform the multiplication first. Perform the addition next. Sequential Execution. R1. Multiplier.
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Pipelining • Applied to sequential steps to speed up operation Example: Compute Ri = AiBi + Ci for i=1, 2, … n Perform the multiplication first Perform the addition next
Sequential Execution R1 Multiplier Adder R2 R3 MUL ADD
Pipelined Execution R1 Multiplier Adder R3 R2 R4 MUL ADD
B3 C4 A4 B4 A2B2+C2 A4B4 A3B3 A2B2 A1B1 C2 C3 A3B3+C3 B2 B1 A3 A2 A1 A1B1+C1 A4B4+C4 C1 Pipelined Execution Clock Input A Input B Input C R1 A1 A2 A3 A4 R2 B1 B2 B3 B4 R3 A1B1 A2B2 A3B3 A4B4 R4 C1 C2 C3 C4 Mult. Adder
Pipelines Clock S1 R1 S2 R2 S3 R3 S4 R4 Input
Pipelines n = number of Tasks k = number of segments T = segment time For n >> k
Pipelining • Non Pipelined Process Execute Fetch Instr. Get Operands Store Result Instr.1 Instr.1 Instr.1 Instr.1 ƮALU ƮMem ƮMem ƮReg Register File PC Instr.Mem. ALU Data Mem.
Pipelining • Non Pipelined Process Execute Fetch Instr. Get Operands Store Result Instr.2 Instr.2 Instr.2 Instr.2 ƮALU ƮMem ƮMem ƮReg Register File PC Instr.Mem. ALU Data Mem.
Pipelining • Non Pipelined Process • Clock Period = • Clocks per Instruction = ƮALU ƮMem ƮMem ƮReg Register File PC Instr.Mem. ALU Data Mem.
Pipelining • Pipelined Process Execute Fetch Instr. Get Operands Store Result Instr.2 Instr.1 Instr.5 Instr.3 Instr.4 Instr.2 Instr.1 Instr.2 Instr.4 Instr.3 Instr.3 Instr.2 Instr.1 Instr.1 ƮALU ƮMem ƮMem ƮReg IR Register File Result PC Instr.Mem. ALU Data Mem. X Y
Pipelining • Pipelined Process IR Register File Result PC Instr.Mem. ALU Data Mem. X Y
Pipelining • Pipelined Process • Clock Period = • Clocks per Instruction = ƮALU ƮMem ƮMem ƮReg IR Register File Result PC Instr.Mem. ALU Data Mem. X Y
Pipelining Hazards • Structural Hazards Hardware can’t support instruction combination at a certain time. Example: IR Register File Result PC Instr.Mem. ALU Data Mem. X Y
Pipelining Hazards • Data Hazards One instruction has to wait for another to complete. Example: IR Register File Result PC Instr.Mem. ALU Data Mem. X Y
Pipelining Hazards • Control Hazards Decision depends on the result of unfinished instruction. Example: IR Register File Result PC Instr.Mem. ALU Data Mem. X Y
Pipelining The End
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