Physical Limitations of Logic Gates – Week 10a

1. A D B C Physical Limitations of Logic Gates – Week 10a • In a computer we’ll have circuits of logic gates to perform specific functions • Computer Datapath: Boolean algebraic functions using binary variables • Symbolic representation of functions using logic gates • Example: • Every node has capacitance and interconnects have resistance. It takes time to charge these capacitances. • Thus, output of all circuits, including logic gates is delayed from input. • For example we will define the unit gate delay

2. D UNIT GATE DELAY D Time delay D occurs between input and output: “computation” is not instantaneous Value of input at t = 0+ determines value of output at later time t = D A C B Logic State Input (A and B tied together) 1 0 t 0 Output 1 t 0 0

3. D UNIT GATE DELAY D in ASYNCHRONOUS LOGIC Time delay D is measured from the last input change A C B Logic State Input A 1 Input B 0 t 0 Output 1 t 0 0

4. CK A C B Synchronous and Asynchronous Logic Time delay occurs between input and output in real logic circuits. Therefore the time at which output appears is difficult to predict… it depends for example on how many gates you go through. We will often not distinguish asynchronous vs synchronous logic. To make logic operations as fast as possible, we need predictability of signal availability. That is we want to know exactly when “C” is correctly computed from A and B. This requirement argues for synchronous logic, in which a clock signal CK actually initiates the computation of C. Thus in the modified gate, C will be valid precisely one gate delay (tD) after the clock input CK, goes high (A and B are evaluated precisely when CK goes high, what they do before or after this is irrelevant; CK must go low, then high again before the NAND gate again looks at A and B).

5. A B D C EFFECT OF GATE DELAY Cascade of Logic Gates Inputs have different delays, but we ascribe a single worst-case delay D to every gate How many “gate delays for shortest path? ANSWER : 2 How many gate delays for longest path? ANSWER : 3 Which path is the important one? ANSWER : LONGEST

6. Note becomes valid one gate delay after B switches Note that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second. No change at t =3 tD TIMING DIAGRAMS A Logic state Show transitions of variables vs time B D t C 0 t tD t tD 2tD t tD t 2tD 3tD tD

7. EXAMPLE WHAT IS THE ORIGIN OF GATE DELAY? Logic gates are electronic circuits that process electrical signals Most common signal for logic variable: voltage Specific voltage ranges correspond to “0” or “1” Thus delay in voltage rise or fall (because of delay in charging internal capacitances) will translate to a delay in signal timing Note that the specific voltage range for 0 or 1 depends on “logic family,” and in general decreases with logic generations

8. inside a large system VOLTAGE WAVEFORMS (TIME FUNCTIONS) Inverter input is vIN(t), output is vOUT(t) Vin(t) t

9. Vin(t) 1.5 t Approximation tD tD tD GATE DELAY (PROPAGATION DELAY) Define  as the delay required for the output voltage to reach 50% of its final value. In this example we will use 3V logic, so halfway point is 1.5V. Inverters are designed so that the gate delay is symmetrical (rise and fall) Vout(t) 1.5 t

10. How fast is this? Speed of light: c = 3  108 m/s Distance traveled in 57 ps is: EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Computer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculations Implication: if clock frequency = 500 MHz clock period = (5108 s1)1 Period = 2  10 9s = 2 ns (nanoseconds) Gate delay must be tD = (1/35)  Period = (2 ns)/35 = 57 ps (picoseconds) C X tD = (3x108m/s)(57x10-12s) = 17 x 10-4 m = 1.7cm

11. WHAT DETERMINES GATE DELAY? The delay is mostly simply the charging of the capacitors at internal nodes. We already know how to analyze this.

12. 5 MODEL Vx R 2.5 II RC = 0.1ns C 5 vIN vOUT 2.5 Vx t tD = 0.069ns Example The gate delay is simply the charging of the capacitors at internal nodes. Oversimplified example using “ideal inverter, II” and 5V logic swing RC = 0.1ns so 0.069ns after vIN switches by 5V, Vx moves 2.5V

13. vIN vOUT VX t tD = 0. 69 RC Simple model for logic delays Model actual logic gate as an ideal logic gate fed by an RC network which represents the dominant R and C in the gate. v ( t ) Ideal Logic gate R Ideal Logic gate OUT VX etc. C Actual Logic Gate v ( t ) IN t

14. How can we build inverters, NAND gates, etc. ? We need some sort of controlled switch: that is a device in which a switch opens or closes in response to an input voltage (a control voltage). If we have a controlled switch it is an easy matter to build inverters, NAND gates, etc. For example an electromagnetic relay has a coil producing a magnetic field causing some contacts to “snap shut” when a voltage is applied to the coil. Lets imagine a simple controlled switch, but include in it some resistance (all real devices have non-zero resistance).

15. I Output I vs. V I R Input high Output Input low + + Input - - Controlled Switch Model V The basic idea: We need a switch which is controlled by an input voltage. For example: Input V = 0 means the switch is open, whereas an input voltage of 2V means that the switch is closed (We will call this a “Type N controlled switch”)

16. + + + + RN - - - - G Output + Input S RP G Output + Input - S Controlled Switch Model Type N controlled switch” means switch is closed if input is high. (VG > VS) - Type P controlled switch” means switch is closed if input is low. (VG < VS) Now lets combine these switches to make an inverter.

17. VDD = 2V - SP is closed if VIN < VDD SP + RP VOUT VIN + + RN Input Output SN is closed if VIN > VSS + SN - - - VSS = 0V Controlled Switch Model of Inverter So if VIN is 2V then SN is closed and SP is open. Hence VOUT is zero. But if VIN is 0V then SP is closed and SN is open. Hence VOUT is 2V.

18. VDD = 2V VIN =2V + VOUT RN - VSS = 0V VDD = 2V - RP VIN =0V + VOUT - - VSS = 0V Controlled Switch Model of Inverter IF VIN is 2V then SN is closed and SP is open. Hence VOUT is zero (but driven through resistance RN). But if VIN is 0V then SP is closed and SN is open. Hence VOUT is 2V (but driven through resistance RP).

19. VDD = 2V VIN =2V + VOUT RN - VSS = 0V VOUT VDD = 2V - VIN jumps from 2V to 0V RP VIN =0V + VIN jumps from 0V to 2V VOUT t - - VSS = 0V Controlled Switch Model of Inverter IF there is a capacitance at the output node (there always is) then VOUT responds to a change in VIN with our usual exponential form.

20. Controlled Switch Model of Inverter We will expand on this model in coming weeks. The controlled switches will of course be MOS transistors. The resistance will be the effective output resistance of the MOS devices. The capacitance will be the input capacitance of the MOS devices. But now lets briefly review the energy used in charging and discharging capacitances so we can start to estimate chip power.

21. CASE 1-Charging R t=0 i  VDD C RD  Power into R Power into C Power out of "battery" ¥ 1 2 = E iV dt CV ò C C DD This must be difference of E and EC, i.e. 2 0 1 = 2 CV DD 2 ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS – A REVIEW Capacitor initially uncharged (Q=CVDD at end) Switch moves @ t=0 Energy into R (heat) Energy into C Energy out of "battery"

22. R t=0  VDD C RD  1 2 CV DD 2 1 = 2 CV DD 2 ENERGY AND POWER IN CHARGING Capacitor initially uncharged (Q=CVDD at end) Switch moves @ t=0 Energy into R (heat) Energy into C Energy out of "battery" In charging a capacitor from a fixed voltage source VDD half the energy from the source is delivered to the capacitor, and half is lost to the charging resistance, independent of the value of R.

23. Power into RD Power out of C Power out of battery ¥ 1 2 = E iV dt CV ò This must be energy initially in C, i.e. C C DD 2 0 Power in/out of R =0 1 = 2 CV DD 2 ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS CASE 2-discharging R t=0 Capacitor initially charged (Q=CVDD) and discharges.  VDD C RD  i Switch moves @ t=0 =0 Energy into RD (heat) Energy out of C Energy out of battery =0

24. 1 2 CV DD 2 1 = 2 CV DD 2 ENERGY IN DISCHARGING CAPACITORS R t=0 Capacitor initially charged (Q=CVDD) and discharges.  VDD C RD  Switch moves @ t=0 Energy out of C Energy into RD (heat) When a capacitor is discharged into a resistor the energy originally stored in the capacitor (1/2 CVDD2) is dissipated as heat in the resistor

25. POWER DISSIPATION in DIGITAL CIRCUITS Each node transition (i.e. charging or discharging) results in a loss of (1/2)(C)(VDD)2 How many transitions occur per second? Well if the node is pulsed up then down at a frequency f (like a clock frequency) then we have 2f dissipation events. A system of N nodes being pulsed at a frequency f to a signal voltage VDD will dissipate energy equal to (N) (2f )(½CVDD2)each second Therefore the average power dissipation is (N) (f )(CVDD2)

26. LOGIC POWER DISSIPATION Power = (Number of gates) x (Energy per cycle) x (frequency) P = (N) (CVDD2)(f ) • N = 107; VDD = 2 V; node capacitance = 10 fF; f = 109 s-1 (1GHz) • P = 400 W! -- a toaster! • Pretty high but realistic • What to do?(N increases, f increases, hmm) • Lower VDD • Turn off the clock to the inactive nodes Clever architecture and design! Lets define a as the fraction of nodes that are clocked (active). Then we have a new formula for power.

27. LOGIC POWER DISSIPATION with power mitigation Power = (Energy per transition) x (Number of gates) x (frequency) x fraction of gates that are active (a). P = a N f CVDD2 In the last 5 years VDD has been lowered from 5V to about 1.5V. It cannot go very much lower. But with clever design, we can make a as low as 1 or 10%. That is we do not clock those parts of the chip where there is no computation being made at the moment. Thus the 400W example becomes 4 to 40W, a manageable range (4W with heat sink, 40W with heat sink plus fan on the chip). “Heat pipe” – can be Used to remove heat From an IC better than A copper heat conductor Hot Cu rod IC Hot IC Hollow heat pipe