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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 2 Jens Rudolf & Johannes Lange. Retrospection. Layout two weeks ago. Current Layout: Implemented Truncation of Bits Carry Save Adder Pipelining Rejected Wallace Booth Algorithm.
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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 2 Jens Rudolf & Johannes Lange
Retrospection • Layout two weeks ago • Current Layout: • Implemented • Truncation of Bits • Carry Save Adder • Pipelining • Rejected • Wallace • Booth Algorithm
Truncation of Bits • Consideration: multiplier influence on area and performance is bigger than adder: • Reduce coefficient to 8 Bits • Reduce input length to 8 Bits
Carry Save Multiplier • 6 Carry Save Adders (CSA) from 13 to 8 bits • 1 Carry Save Subtractor (CSS) with 7 Bits • 1 Ripple Carry Adder (RCA) with 7 Bits • Pipeline Stages: 2
Overview • Additional 1 bit shifter for carry array • Multiplier: 2 Pipeline Stages • Overall: 4 Pipeline Stages
Result • Big optimization influence of Xilinx ISE • Biggest improvement by truncation and pipelining • Possible performance improvement by Carry Select Adder instead of Ripple Carry