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LAL/LPNHE work for the AIDA WP3

LAL/LPNHE work for the AIDA WP3. A. Lounis, G. Martin-Chassard, D. Thienpont, J. Tongbong (LAL) G. Calderini, J-F. Genat (LPNHE). November 29, 2012. LAL/LPNHE project status. 3D (Tezzaron) OMEGAPIX2 chip delayed Submitted in October 2011, not received yet

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LAL/LPNHE work for the AIDA WP3

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  1. LAL/LPNHE work for the AIDA WP3 A. Lounis, G. Martin-Chassard, D. Thienpont, J. Tongbong (LAL) G. Calderini, J-F. Genat (LPNHE) November 29, 2012

  2. LAL/LPNHE project status • 3D (Tezzaron) OMEGAPIX2 chip delayed • Submitted in October 2011, not received yet • Pixel matrix sensor received and tested • A new OMEGAPIX chip in 65 nm techno as an alternative to the 3D chip • Same pixel form factor: 35x200 μm • New analog front-end (LAL), new digital pixel (LPNHE) • TSMC 65 nm techno • 3x1z1u metal stack (RF, CRN65LP), 6 metal layers + RDL • tcbn65lp standard cells library • In waiting for the common PDK provided by CERN

  3. Analog front-end • A very classical architecture with preamp, shaper and comparator is designing Threshold Gain = 2 Gain = 65 mV/fC Cf = 15 fF (mimcap) Leakage I absorption Vref + local DAC

  4. Simulations performances • Typical Low Power transistor • Cf = 15 fF => 66 mV/fC • with Cd = 300 fF, ENC from 150 e- to 166 e- when leakage current varies from 0 to 100 nA • Preamp Open Loop gain = 90 dB • Global power consumption: vdd = 1.2 V and I = 8 μA => 9.6 μW • Dynamic range: 450 mV max. • 2.5 V transistor • Cf = 15 fF => 66 mV/fC • With Cd = 300 fF, ENC from 128 e- to 150 e- • Preamp Open Loop gain = 90 dB • Global Power consumption: vdd = 2.5 V and I = 8 μA => 20 μW • Dynamic range: 1 V • DAC • Not yet, which resistor can be used ?

  5. « Digital » pixel • Means digital processing in each pixel • tcbn65lp standard cell library • Developing by LPNHE

  6. Charge Pump PLL • Featured with a digital phase detector and a charge pump • Advantages • Fast lock and tracking • Fully integrated • Low power and jitter • PLL in 0.35 um AMS to understand general principle Kvco = 1300Mhz/V

  7. Status • We have installed the 65 nm PDK of TSMC • Provided by Europractice • First preliminary design: analogue (LAL) and digital (LPNHE) • PLL design • Waiting for the 3D OMEGAPIX2 chip designed in GF/Tezzaron techno…, MPW by CMP

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