“programmable Pattern generator” mid-term presentation

1. “programmable Pattern generator”mid-term presentation Students : Or Shperling & Liron Ulman Instructor : Ina Rivkin

2. System Controller Stop Our design Start Trigger in CONFIG ML605 Board Trigger Out DATA Receiver : Analogue Pre- Processing D/A D/A D/A D/A A/D DSP Low Frequency

3. Project’s Goals & Definitions • Designing an On-Line configurable “Pattern Generator” using 2 implementations: (1) Xilinx IP-Core DDS (Direct Digital Synthesizer). (2) A memory which will be use as a LUT for the pattern values, with a logic which will govern the memory output. • User’s trigger will initiate sine output. • Test the implementations on ML605 platform.

4. Project’s requirements (1) • Configuration phase- Inserting required Frequency and initial phase. • ‘Start’ initiates system iteration. Some delay after ‘Start’, our system is ready for trigger. • ‘Trigger in’ is 1KHz PRI [Pulse Repetition Interval]. • 1st ‘Trigger in’ initiates 4 channels of sine signal with different frequency and different phase. • Every ‘Trigger in’ reset the phase of all channels to the initial phase. • ‘Stop’ means : “End of current iteration”.

5. Project’s requirements (2) • Trigger_out is an output for the A/D to inform the Sine is ready. • Trigger_out(t) = Trigger_in (t – (T1 + TDM ))T1 = Our module delay from triggerTDM = Analogue receiver delay • At least 32 sampling points per sine period. • Data width according to D/A width – typically 24 bits.

6. Frequencies analysis • Signal resolution and clock frequency dictates maximal sine frequency : • Our clock is produced by a DCM unit which is fed by 66 MHz board crystal’s “User Clock”. • We’ve examined some clock frequency till satisfactory results have been achieved.

7. Implementation • First Implementation – using a built-in library unit- Direct Digital Synthesizer (DDS)- to compute the sine. • Second Implementation- our own implementation and logic design, using memory units and logic.

8. DDS Design’s high level X4 PHASE_OUT CE CE PHASE_OUT[0..4] START SINE SCLR SCLR DDS Module SINE[0..23] TRIG_IN WE WE RDY RDY REG_SELECT REG_SELECT RESET DATA[0..4] CONFIG STATE CLK STOP Controller STATE CLK_IN DCM CLK_OUT Programmable Delay TRIG_OUT TRIG_IN

9. Controller States Machine Config Wait for Trig State= “001” CE = ‘1’ Idle WE = ‘1’ State= “010” CE = ‘1’ Start = ‘1’ Config= ‘1’ SCLR=‘1’ State= “000” CE = ‘0’ Trig=‘1’ Reset Phase Run Stop = ‘1’ State= “100” State= “011” Trig = ‘1’ SCLR=‘1’ CE = ‘1’ CE = ‘1’

10. Frequency testing -200 MHz clock, sampled at 400 MHz – runs on board Sine is too noisy.

11. 132 MHz clock, sampled at 264 MHz – runs on board Noise exists but is not significant – good enough.

12. Conclusions • Maximal frequency is : • Applying higher frequency will be possible only if we trade-off resolution or suffering significant signal noise at the D/A’s inputs.

13. Logic simulation

14. Sine generator – Memory implementation 0x0000000 • Whole sine information found within ¼ of a period. • Addresses jump will be determined by initialized frequency. • Initial address will be determined by initialized phase 0x0000004 0x0000008 Sine

15. Memory implementation – General Design X4 PHASE_OUT PHASE_OUT[0..4] START SINE SINE[0..23] TRIG_IN Memory RDY From User Control signals RESET ADDRESS CONFIG STATE CLK STOP Controller STATE Frequency Addresses counter From User Address Phase

16. Action Items from PDR • ML605 board interface with “outer world” : (1) 2 Mezzanine connectors, FMC-LPC, FMC-HPC, can handle 250 MHz LVDS. (2) No Serializer - Deserializer (SerDes) is available.

17. 2x FPGA Mezzanine Card (FMC) connector

18. Current Status • Final phases of DDS implementation – successful logic simulation with 4 channels. Now- board implementation • One channel was tested successfully on board

19. Gantt Chart Mid Term 14/4/2013 Final 1/7/2013