William Stallings Computer Organization and Architecture 6 th Edition

1. William Stallings Computer Organization and Architecture6th Edition Chapter 7 Input/Output

2. Input/Output Problems • Why one does not connect peripherals directly to the system bus? • Wide variety of peripherals • Delivering different amounts of data • At different speeds • In different formats • All slower than CPU and RAM • Need I/O modules

3. Input/Output Module • The I/O module has two major functions: • Interface to CPU and Memory • Interface to one or more peripherals

4. Generic Model of I/O Module 透過系統匯流排和CPU或記憶體聯絡 透過適當的資料線和週邊聯絡

5. External Devices • Three Types of external devices • Human readable • Suitable for communicating with the computer user • E.g. Screen, printer, keyboard • Machine readable • Suitable for communicating with equipment. • E.g. Monitoring and control • Communication • Suitable for communicating with remote devices • E.g. Modem • Network Interface Card (NIC)

6. External Device Block Diagram Convert data from electrical to other forms Control the device’s operation in response to direction from the I/O module

7. The interface to the I/O module • Control signals • Determine the function that the device will perform • E.g. INPUT/ OUTPUT, READ/WRITE • Data • A set of bits to be sent to or received from the I/O module. • Status signals • Indicate the state of the device • E.g. : READY / NOT-READY, BUSY

8. Typical I/O Data Rates

9. I/O Module Function • The major functions/requirements for I/O • Control & Timing • To coordinate the flow of traffic between internal resources and external devices. • CPU Communication • The I/O module must communicate with the processor and with the external device • Device Communication • The communication involves commands, status information, and data. (see Fig. 7.2) • Data Buffering • The data are buffered in the I/O module and then sent to the peripheral device. • Error Detection

10. I/O Steps • Transfer date from external device to the CPU • CPU checks I/O module device status • I/O module returns status • If ready, CPU requests data transfer • I/O module gets data from device • I/O module transfers data to CPU • Variations for output, DMA, etc.

11. CPU Communication • CPU communication involves the following: • Command decoding • The I/O module accepts commands from the processor (by control bus) • Data exchange • Data are exchanged between the CPU and the I/O module over the data bus • Status reporting • E.g. BUSY and READY • Address recognition • Recognize one unique address foreach peripheral it controls • Device Communication • Commands, status information, and data (see Fig. 7.2)

12. Block Diagram of an I/O Module

13. I/O Module Structure • Hide or reveal device properties to CPU • The I/O module may hide the details of timing, formats, and the electro-mechanics of an external device so that the processor can function in terms of simple read and write commands. • Support multiple or single device • Control device functions or leave for CPU • Also O/S decisions • e.g. Unix treats everything it can as a file • Types of I/O module • I/O channel or I/O processor • Take on most of the detailed processing burden, presenting a high-level interface to the CPU. • I/O controller or device controller • Quite primitive and requires detailed control.

14. Input Output Techniques • Programmed I/O • Data are exchanged between the processor and the I/O module. • The processor executes a program that gives it direct control of the I/O operation. • When the processor issues a command to the I/O module, it must wait until the I/O operation is complete. • Interrupt driven I/O • The processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when the latter has completed its work • Direct Memory Access (DMA) • The I/O module and main memory exchange data directly, without processor involvement.

15. The techniques for Input of a Block of Data

16. Programmed I/O • CPU has direct control over I/O • Sensing status • Read/write commands • Transferring data • CPU waits for I/O module to complete operation • Wastes CPU time

17. Programmed I/O - detail • CPU requests I/O operation • I/O module performs operation • I/O module sets status bits • CPU checks status bits periodically • I/O module does not inform CPU directly • I/O module does not interrupt CPU • CPU may wait or come back later

18. I/O Commands • To execute an I/O instruction, the CPU issues an address and an I/O command. • CPU issues address • Identifies module (& device if >1 per module) • Specifying the particular I/O module and external device. • CPU issues command • Control - telling module what to do • Used to activate a peripheral and tell it what to do. • e.g. spin up disk • Test - check status • Used to test various status conditions associated with I/O module and its peripherals. • e.g. power? Error? • Read/Write • Module transfers data via buffer from/to device

19. Addressing I/O Devices • Under programmed I/O data transfer is very like memory access (CPU viewpoint) • Each device given unique identifier • When the CPU issue an I/O command, the command contains the address of the desired device. • Each I/O module must interpret the address lines to determine if the command is for itself.

20. I/O Mapping • When the CPU, main memory, and I/O share a common bus, two modes of addressing are possible. • Memory mapped I/O • Devices and memory share an address space • I/O looks just like memory read/write • No special commands for I/O • Large selection of memory access commands available • Isolated I/O • Separate address spaces • Need I/O or memory select lines • Special commands for I/O • Limited set

21. Memory-Mapped and Isolated I/O Example:從keyboard讀1 byte的資料進入CPU的累積器中 10bit address (512bit memory, 512 I/O address) address 516 is data register, 517 is status register

22. Interrupt Driven I/O • Overcomes CPU waiting • No repeated CPU checking of device • I/O module interrupts when ready

23. Interrupt Driven I/OBasic Operation • CPU issues read command • I/O module gets data from peripheral while CPU does other work • I/O module interrupts CPU • CPU requests data • I/O module transfers data

24. Simple Interrupt Processing

25. Interrupt Processing • When an I/O device completes an I/O operation • The device issue an interrupt signal to the CPU. • The CPU finishes execution of the current instruction. • The CPU tests for an interrupt. Sends an acknowledgement signal to the device that issued the interrupt. • The CPU now needs to prepare to transfer control to the interrupt routine. • To save information needed to resume the current program at the point of interrupt. • Program Status Word (PSW) • Program Counter (PC) • The CPU now loads the PC with the location of interrupt-handling program

26. Interrupt Processing • The interrupt handler processes the interrupt. • When the interrupt processing is complete, the saved register values are retrieved from the stack and stored to the registers. • To restore the PSW and PC values from the stack.

27. Changes in Memory and Register for an Interrupt 4. 更新PC為ISR位址 2. 將PC及相關register的值存到control stack中 5.將儲存在stack中的資料回存到相關register 1. 在address N發生中斷 3. 更新stack pointer 6. 更新stack pointer

28. CPU Viewpoint • Issue read command • Do other work • Check for interrupt at end of each instruction cycle • If interrupted:- • Save context (registers) • Process interrupt • Fetch data & store

29. Design Issues • How do you identify the module issuing the interrupt? • How do you deal with multiple interrupts? • i.e. an interrupt handler being interrupted

30. Identifying Interrupting Module (1) • Device Identification: • Multiple interrupt lines • Different line for each module • Limits number of devices • Software poll • CPU asks each module in turn • Slow (time consuming) • Daisy Chain (Hardware poll, vectored) • Interrupt Acknowledge sent down a chain • Module responsible places vector on bus • CPU uses vector to identify handler routine • Bus Arbitration (vectored) • Module must claim the bus before it can raise interrupt • e.g. PCI & SCSI

31. Multiple Interrupts • Each interrupt line has a priority • Higher priority lines can interrupt lower priority lines • If bus mastering only current master can interrupt

32. Example - PC Bus • 80x86 provides a interrupt request and a Interrupt acknowledge • Interrupt Request (INTR) • Interrupt Acknowledge (INTA) • 8086 based systems use one Intel 82C59A interrupt controller • The objective of the 82C59A is the management of interrupts. • 82C59A has 8 interrupt lines • A 82C59A can handle up to 8 module.

33. Sequence of Events • 8259A accepts interrupts from attached modules. • 8259A determines which module has the higest priority • 8259A signals 8086 (raises INTR line) • CPU Acknowledges via the INTA • 8259A puts correct vector on data bus • CPU processes interrupt

34. The 82C59A is programmable. • The 80386 determines the priority scheme to be used by setting a control world in the 82C59A. • Fully nested • Rotating • Special mask

35. ISA Bus Interrupt System • ISA bus chains two 8259As together • Link is via interrupt 2 • Gives 15 lines • 16 lines less one for link • IRQ 9 is used to re-route anything trying to use IRQ 2 • Backwards compatibility • Incorporated in chip set

36. 82C59A InterruptController

37. Intel 82C55A Programmable Peripheral Interface • The 82C55A is a single-chip general-purpose I/O module

38. Using 82C55A To Control Keyboard/Display

39. Direct Memory Access • Interrupt driven and programmed I/O require active CPU intervention • Transfer rate is limited • CPU is tied up in managing an I/O transfer. • When large volumes of data are to be moved, a more efficient technique is required: • DMA is the answer

40. DMA Function • DMA involves an additional module (hardware) on system bus. • DMA controller is capable of mimicking the processor takes over from CPU for I/O. • The DMA module must use the bus only when the CPU does not need bus. • The DMA module must force the CPU to suspend operation temporarily. • Burst transfer • 將含有一長串記憶字的區段不間斷的一次傳輸完成。 • Cycle stealing • 只允許DMAC一次傳送一個資料字。

41. DMA Module Diagram

42. DMA Operation • When CPU wishes to read/ write a block of data CPU tells DMA controller: • Read/Write control lines • Device address • Starting address of memory block for data • Amount of data to be transferred • CPU carries on with other work • DMA controller deals with transfer • Without going through the CPU. • DMA controller sends interrupt when finished

43. DMA Transfer: Cycle Stealing • DMA controller takes over bus for a cycle • Transfer of one word of data • Not an interrupt • CPU does not switch context • CPU suspended just before it accesses bus • i.e. before an operand or data fetch or a data write • Slows down CPU • DMA is far more efficient than interrupt-driven or programmed I/O

44. DMA and Interrupt Breakpoints during an Instruction Cycle 當CPU要使用匯流排之前需暫停一個bus cycle,讓DMAC傳送1 word之後，才將bus控制權交回給CPU。

45. DMA Configurations (1)- Single-bus, detached DMA • Share the same system Bus • Uses programmed I/O to exchange data between memory and an I/O module through the DMA controller. • Each transfer uses bus twice • I/O to DMA then DMA to memory • CPU is suspended twice

46. DMA Configurations (2)-Single-bus, integrated DMA-I/O • Single Bus, Integrated DMA controller • Controller may support >1 device • Each transfer uses bus once • DMA to memory • CPU is suspended once

47. DMA Configurations (3) • Separate I/O Bus • Bus supports all DMA enabled devices • Each transfer uses bus once • DMA to memory • CPU is suspended once

48. The evolution of the I/O Function • 1. The CPU directly controls a peripheral device. • 2. A controller or I/O module is added. • The CPU use programming I/O without interrupt. • 3. The same configuration as in step 2, but interrupts are employed. • The CPU need not spend time waiting for an I/O operation to be performed. • 4. Direct Memory Access, DMA • Moving a block of data to or from memory without involving the CPU. • 5. I/O Channel • The I/O module is enhanced to become a processor in its own right, with a specialized instruction set tailored for I/O • 6. I/O Processor • The I/O module has a local memory of its own and is a computer in its own right.

49. I/O Channels • An I/O channel has the ability to execute I/O instruction, which gives it complete control over I/O operation. • I/O devices getting more sophisticated • e.g. 3D graphics cards • CPU instructs I/O controller to do transfer • I/O controller does entire transfer • Improves speed • Takes load off CPU • Dedicated processor is faster

50. I/O Channel Architecture 選擇器用於控制高速裝置，一次僅能處理一個I/O運算 多工器可與多個慢速或低速之裝置相連，並且可與數個I/O裝置同時運作。