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CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week)

CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week). Section 1: Mary Jane Irwin ( www.cse.psu.edu/~mji ) Section 2: Feihui Li ( www.cse.psu.edu/~feli ) Course material on ANGEL: cms.psu.edu [ adapted from D. Patterson slides ]. Head’s Up. Last week’s material

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CSE 331 Computer Organization and Design Fall 2006 Week 11&12 (Thanksgiving Week)

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  1. CSE 331Computer Organization and DesignFall 2006Week 11&12 (Thanksgiving Week) Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji) Section 2: Feihui Li (www.cse.psu.edu/~feli ) Course material on ANGEL: cms.psu.edu [adapted from D. Patterson slides]

  2. Head’s Up • Last week’s material • Designing a MIPS single cycle datapath • This week’s material • Multicycle MIPS datapath implementation, microprogramming • Reading assignment –  PH: 5.5, 5.7, B.10, C.3-C.5

  3. Review: Single Cycle Data and Control Path Instr[25-0] 1 Shift left 2 28 32 26 0 PC+4[31-28] 0 Add Add 1 4 Shift left 2 PCSrc Jump ALUOp Branch MemRead Instr[31-26] Control MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] 0 Read Data 1 ALU Write Addr Read Data 2 0 1 Write Data 0 Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

  4. Cycle 1 Cycle 2 Clk lw sw Waste Single Cycle Disadvantages & Advantages • Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instr • especially problematic for more complex instructions like floating point multiply • May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but • It is simple and easy to understand

  5. Multicycle Implementation Overview • Each instruction step takes 1 clock cycle • Therefore, an instruction takes more than 1 clock cycle to complete • Not every instruction takes the same number of clock cycles to complete • Multicycle implementations allow • faster clock rates • different instructions to take a different number of clock cycles • functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result • only need one memory • only need one ALU/adder

  6. IR A ALUout B MDR The Multicycle Datapath – A High Level View • Registers have to be added after every major functional unit to hold the output value until it is used in a subsequent clock cycle Address Memory Read Addr 1 PC Read Data 1 Register File Read Addr 2 Read Data (Instr. or Data) ALU Write Addr Write Data Read Data 2 Write Data

  7. System Clock clock cycle MemWrite RegWrite IR Address Memory Read Addr 1 A PC Read Data 1 Register File Read Addr 2 Read Data (Instr. or Data) ALUout ALU Write Addr Write Data Read Data 2 B Write Data MDR Clocking the Multicycle Datapath

  8. Multicycle Approach • Break up the instructions into steps where each step takes a clock cycle while trying to • balance the amount of work to be done in each step • use only one major functional unit per clock cycle • At the end of a clock cycle • Store values needed in a later clock cycle by the current instruction in a state element (internal register not visible to the programmer) IR – Instruction Register MDR – Memory Data Register A and B – Register File read data registers ALUout – ALU output register • All (except IR) hold data only between a pair of adjacent clock cycles (so they don’t need a write control signal) • Data used by subsequent instructions are stored in programmer visible state elements (i.e., Register File, PC, or Memory)

  9. MDR The Complete Multicycle Data with Control PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  10. Review: Our ALU Control • Controlling the ALU uses of multiple decoding levels • main control unit generates the ALUOp bits • ALU control unit generates ALUcontrol bits

  11. Multicycle Approach, con’t • Reading/writing to • any of the internal registers or the PC occurs (quickly) at the end of a clock cycle • reading/writing to the Register File takes ~50% of a clock cycle since it has additional control and access overhead (reading can be done in parallel with decode) • Had to add multiplexors in front of several of the functional unit inputs because the functional unit input ports have multiple inputs since they are now shared by different clock cycles • All operations occurring in one clock cycle occur in parallel • This limits us to one ALU operation, one memory access, and one Register File access per clock cycle

  12. Five Instruction Steps • Instruction Fetch • Instruction Decode and Register Fetch • R-type Instruction Execution, Memory Read/Write Address Computation, Branch Completion, or Jump Completion • Memory Read Access, Memory Write Completion or R-type Instruction Completion • Memory Read Completion (Write Back) INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!

  13. Step 1: Instruction Fetch • Use PC to get instruction from the memory and put it in the Instruction Register • Increment the PC by 4 and put the result back in the PC • Can be described succinctly using the RTL "Register-Transfer Language“ IR = Memory[PC]; PC = PC + 4; Can we figure out the values of the control signals? What is the advantage of updating the PC now?

  14. MDR Datapath Activity During Instruction Fetch PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  15. 00 MDR Datapath Activity During Instruction Fetch PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  16. Fetch Control Signals Settings Instr Fetch IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X Start

  17. Step 2: Instruction Decode and Register Fetch • Don’t know what the instruction is yet, so can only • Read registers rs and rt in case we need them • Compute the branch address in case the instruction is a branch • The RTL: A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC +(sign-extend(IR[15-0])<< 2); • Note we aren't setting any control lines based on the instruction (since we don’t know what it is (the control logic is busy "decoding" the op code bits))

  18. MDR Datapath Activity During Instruction Decode PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  19. 00 MDR Datapath Activity During Instruction Decode PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  20. Decode Control Signals Settings Decode IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 Start

  21. Step 3 (instruction dependent) • ALU is performing one of four functions, based on instruction type • Memory reference (lw and sw): ALUOut = A + sign-extend(IR[15-0]); • R-type: ALUOut = A op B; • Branch: if (A==B) PC = ALUOut; • Jump: PC = PC[31-28] || (IR[25-0] << 2);

  22. MDR Datapath Activity During Instruction Execute PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  23. 00 MDR Datapath Activity During lw & sw Execute PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  24. MDR Datapath Activity During R-type Execute PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  25. 10 MDR Datapath Activity During R-type Execute PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  26. Datapath Activity During R-type Completion PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 MDR 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  27. MDR Datapath Activity During beq Execute PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  28. 01 MDR Datapath Activity During beq Execute PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  29. MDR Datapath Activity During j Execute PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  30. MDR Datapath Activity During j Execute PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  31. Execute Control Signals Settings Decode IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 Start (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 PCSource=10 PCWrite Execute

  32. The x86 is an extremely complex instruction set architecture, and most of that complexity is embedded in the microcode. ... Every time the microarchitecture must be changed, so must the microcode, and all fundamental changes to either will expose new areas in the microcode for which the past is a poor guide to correctness. The Pentium Chronicles, Colwell, pg. 66

  33. Step 4 (also instruction dependent) • Memory reference: MDR = Memory[ALUOut]; -- lwor Memory[ALUOut] = B;-- sw • R-type instruction completion Reg[IR[15-11]] = ALUOut; • Remember, the register write actually takes place at the end of the cycle on the clock edge

  34. MDR Datapath Activity During Memory Access PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  35. Datapath Activity During lw Memory Access PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 MDR 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  36. Datapath Activity During sw Memory Access PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 MDR 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  37. MDR Datapath Activity During R-type Completion PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  38. Memory Access Control Signals Settings Decode IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 Start (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 PCSource=10 PCWrite Execute (Op = lw) (Op = sw) Memory Access RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 MemRead IorD=1 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0

  39. Step 5: Memory Read Completion (Write Back) • All we have left is the write back into the register file the data just read from memory for lw instruction Reg[IR[20-16]]= MDR; What about all the other instructions?

  40. MDR Datapath Activity During lw Write Back PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  41. MDR Datapath Activity During lw Write Back PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 0 1 Address Memory 0 PC 0 Read Addr 1 A Read Data 1 IR Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) 0 ALUout ALU Write Addr Write Data 1 Read Data 2 B 0 1 Write Data 4 1 0 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

  42. Write Back Control Signals Settings Decode IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 Start (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 PCSource=10 PCWrite Execute (Op = lw) (Op = sw) Memory Access RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 MemRead IorD=1 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 RegDst=0 RegWrite MemtoReg=1 PCWriteCond=0 Write Back

  43. RTL Summary

  44. Answering Simple Questions • How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label #assume not add $t5, $t2, $t3 sw $t5, 8($t3)Label: ... • What is going on during the 8th cycle of execution? • In what cycle does the actual addition of $t2 and $t3 takes place? • In what cycle is the branch target address calculated? 5 5 3 4 4 = 21 cycles address for second lw being calculated 16th cycle 12th cycle

  45. Datapath control points . . . Combinational control logic . . . . . . State Reg Inst Opcode Next State Multicycle Control • Multicycle datapath control signals are not determined solely by the bits in the instruction • e.g., op code bits tell what operation the ALU should be doing, but not what instruction cycle is to be done next • We can use a finite state machine for control • a set of states (current state stored in State Register) • next state function (determined by current state and the input) • output function (determined by current state) • So we are using a Moore machine (datapath control signals based only on current state)

  46. Multicycle Datapath Finite State Machine Decode 0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch 1 Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 Start (Op = R-type) (Op = beq) 2 (Op = lw or sw) (Op = j) 6 8 9 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 PCSource=10 PCWrite Execute (Op = lw) (Op = sw) 3 5 7 Memory Access RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 MemRead IorD=1 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 4 RegDst=0 RegWrite MemtoReg=1 PCWriteCond=0 Write Back

  47. Finite State Machine Implementation PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg Combinational control logic PCSource Outputs ALUOp ALUSourceB ALUSourceA RegWrite RegDst Inputs Op5 Op4 Op3 Op2 Op1 Op0 Next State State Reg Inst[31-26] System Clock

  48. Datapath Control Outputs Truth Table

  49. Next State Truth Table

  50. Simplifying the Control Unit Design • For an implementation of the full MIPS ISA instr’s can take from 1 clock cycle to 20+ clock cycles • resulting in finite state machines with hundreds to thousands of states with even more arcs (state sequences) • Such state machine representations become impossibly complex • Instead, can represent the set of control signals that are asserted during a state as a low-level control “instruction” to be executed by the datapath microinstructions • “Executing” the microinstruction is equivalent to asserting the control signals specified by the microinstruction

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