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Research Work in Tsinghua University EDA Lab (2001-2003)

Summary of research work conducted in the Tsinghua University EDA Lab from 2001 to 2003, including topics such as synthesis and verification, floorplanning and interconnect planning, power distribution network optimization, global routing, and parasitic extraction.

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Research Work in Tsinghua University EDA Lab (2001-2003)

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  1. IC-SOC Workshop (2001-2003)Summary of Research Work in Tsinghua University EDA Lab. Department of Computer Science and Technology Tsinghua University Beijing, 100084, China

  2. 1. Synthesis & Verification • Hardware/Software Partition: • Propose a SSS based H/S partition algorithm (ASICON2003) • better solution than SA and less runtime than Tabu • High-level Synthesis: • Re-synthesis algorithm after floorplanning for timing optimization (ASICON2003) • Based on initial scheduling do floorplanning • After floorplanning do re-scheduling and re-allocation by force-balance method • Controller Synthesis: • A Heuristic State Minimization Algorithm For Incompletely Specified Finite State Machine (ASICON2003, JCST) EDA Lab., Tsinghua Univ.

  3. 2. Floorplanning & Interconnect Planning • Based on proposed Corner Block List (CBL) representation propose several Extended Corner Block List, ECBL, CCBL and SUB-CBL to speed up floorplanning and handle more complicate L/T shaped and rectilinear shaped blocks. • Propose floorplanning algorithms with some geometric constraints, such as boundary, abutment, L/T shaped blocks. • Propose integrated floorplanning and buffer planning algorithms with consideration of congestion . • Using research results from UCLA on interconnect planning • About 30 papers published in DAC, ICCAD, ISPD, ASPDAC, ISCAS and Transactions. EDA Lab., Tsinghua Univ.

  4. 3. P/G Network Analysis & Optimization • Propose anArea Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques (ICCAD2001, accepted by IEEE Trans. On CAD) • Propose a decoupling capacitance optimization algorithm for Robust On-Chip Power Delivery (ASPDAC2004, ASICON2003) 4. Global Routing & Special Routing • Propose several congestion, timing, and both timing and congestion optimization global routing algorithms • Papers were published in ASPDAC, ISCAS, and IEEE Transactions. EDA Lab., Tsinghua Univ.

  5. 5. Parasitic R/L/C Etraction • 3-D R/C Extraction using Boundary Element Method (BEM) • Quasi-Multiple Medium (QMM) BEM algorithms • Hierarchical Block BEM (HBBEM)technique • Fast 3-D Inductance Extraction (FIE) • Papers were published in ASPDAC, ASICON and IEEE Transaction on MTT EDA Lab., Tsinghua Univ.

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