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Data Object

Data Object. Object Types A VHDL object consists of one of the following: Signal, Which represents interconnection wires that connect component instantiation ports together. Variable, Which is used for local storage of temporary data, visible only inside a process.

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Data Object

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  1. Data Object Object Types A VHDL object consists of one of the following: Signal, Which represents interconnection wires that connect component instantiation ports together. Variable, Which is used for local storage of temporary data, visible only inside a process. Constant, which names specific values.

  2. Objects • Objects are used to represent & store the data in the system being described in VHDL. • Object contains a value of a specific type. • The name given to object is called identifier. • Each object has a type & class. • Class indicates how the object is used in the model & what can be done with the object. • Type indicates what type of data the object contains.

  3. Signal • Signal objects are used to connect entities together to form models. • Signals are the means for communication of dynamic data between entities. • A signal declaration looks like this: Signal Signal_name : Signal_type [:= initial_value] The Keyword SIGNAL is followed by one or more signal names.

  4. Each Signal name creates a new signal. • Separating the signal names from the signal type is colon. • Signal type specifies the data type of the information that the signal contains. • The signal can contain an initial value specifier so that the signal value may initialized. • Signals can be declared in entity declaration sections, architecture declarations and package declarations.

  5. Signals in package declaration are also referred to as global signals because they can be shared among entities. • Each signal has a history of values I.e. holds a list of values which include current value of signal & set of possible future values that are to appear on the signal. • Computed value is assigned to signal after delay called ‘delta delay’.

  6. Example : Signal library ieee; use ieee.std_logic_1164.all; entity signal_example is port ( a : in std_logic_vector(7 downto 0); y : out std_logic ); end signal_example;

  7. architecture behave_signal of signal_example is signal temp : std_logic; begin process (a) begin temp <= '1'; for i in 0 to 7 loop temp <= temp xor a(i); end loop; y <= temp; end process; end behave_signal;

  8. Waveform • Waveform show one input only

  9. Variable • Variable are used for local storage in process statements and subprograms. • All assignment to variable occur immediately. • A variable declaration looks like this: Variable variable_name: variable_type [: value]

  10. The keyword VARIABLE is followed by one or more variable names. • Each name creates a new variable. • The construct variable_type defines the data type of the variable, and an optional initial value can be specified. • Variable can be declared in the process declaration and subprogram declaration sections only.

  11. Variable are inherently more efficient because assignments happen immediately, while signals must be scheduled to occur. • Variables take less memory, while signals need more information to allow for scheduling and signal attributes. • Using a Signal would have required a WAIT statement to synchronize the signal assignment to the same execution iteration as the usage.

  12. Example - Variable library ieee; use ieee.std_logic_1164.all; entity variable_example is port ( a : in std_logic_vector(7 downto 0); y : out std_logic ); end variable_example;

  13. architecture behave_variable of variable_example is begin process (a) variable temp: std_logic; begin temp := '0'; for i in 0 to 7 loop temp := temp xor a(i); end loop; y <= temp; end process; end behave_variable;

  14. Signal vs Variables • A Signal has three properties attached to it: type, value and time. while a variable has only two properties attached to it type and value. • Use signals as channels of communication between concurrent statement. In non-synthesizeable models, avoid using signals to describe storage elements. Use variable instead. • Signals occupy about two orders of magnitude more storage than variable during simulation. Signals also cost a performance penalty due to the simulation overhead necessary to maintain the data structures representing signals.

  15. Constants • Constant objects are names assigned to specific values of a type. • Constants give the designer the ability to have a better-documented model, and a model that is easy to update. • Constant declaration : Constant constant_name : type_name [:value];

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