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From Compaq, ASP-DAC00

From Compaq, ASP-DAC00. Power Consumption. Power consumption is on the rise due to: - Higher integration levels (more devices & wires) - Rising clock frequencies - Leakage current becomes appreciable with small V t ’s How does interconnect fit in?

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From Compaq, ASP-DAC00

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  1. From Compaq, ASP-DAC00

  2. Power Consumption • Power consumption is on the rise due to: • - Higher integration levels (more devices & wires)- Rising clock frequencies- Leakage current becomes appreciable with small Vt’s • How does interconnect fit in? • Longer total wirelength contributes to additional wiring capacitance • - NTRS 97 predicts total wirelength of 5 km in 0.1 mm

  3. Simplified power analysis CV2f = S*S2*(1/S) = S2 • Look at scaling of each component of dynamic power (within a block of gates) • Frequency scales up as 1/S (S ~ 0.7 for a typical process shrink) • Voltage decreases ~ S • Capacitance drops as S • Device -- Junction scales as S (perimeter term dominant) Oxide capacitance scales as S2/S = S • Wire -- Pitch ~ S Block Size ~ S2 Total wirelength ~ Block Size / Pitch = S • Normalized to block size, this represents a constant power density • This analysis makes many approximations yet arrives at a similar conclusion to a more complex analysis (Sylvester, ICCAD 98)

  4. Global Net Global Pin 50,000 Gate Module Power Analysis: Global Interconnect Number of global nets is determined using Rent’s Rule to calculate # of global pins, and convert to nets pglobal ~ 0.45 to 0.55 (or plocal - 0.1) Assume buffering of all global wires Nbuffer is estimated by Ltotal / Lcrit

  5. BACPAC Results: Microprocessor • Power could be limiting factor at sub-0.1 mm • Amount of memory greatly impacts total power dissipation (70% assumed here)

  6. Pbump Dc/2 Itop Power Distribution: IR Drop • Grid structure yields low IR drops but wirebonding constrains power to be supplied from chip periphery • Middle of die sees large IR drops due to Dc/2 maximum wirelengthTop layer voltage drop is given by: • With flip-chip, worst-case resistive path drops from Dc/2 to Pbump (bump pad pitch, ~ 200 mm) Compared to IBM S/390 (flip-chip), expression (max) = 32 mV, experiment (avg) = 23 mV

  7. Leakage Power Leakage can be calculated based on the following expression Source: Intel, DAC98 For Vt < 0.2V, leakage becomes significant SOI - reduces 95 mV to ~60 mV

  8. Ipeak tbase Vtn < Vin < Vdd - |Vtp| Short-Circuit Power Extend Veendrick’s method by using Alpha-power law to find peak current BACPAC results indicate that short-circuit power is ~ 10-15% of dynamic power (excluding clock, memory, I/O)

  9. Technology Trends: Power Distribution • Despite dropping power supplies • Rise in power – large supply currents drawn • Larger chips and smaller wires – IR drop Ref: Compaq, ASP-DAC00

  10. Where are we headed ? • Battery weight, • size & lifetime • Cost & sophistication • of heat removal • Device reliability NiCd energy capacity: 10 - 22 W-hrs/lb. Ref: Meindl

  11. SIA Projections on Vdd Scaling Ref: Meindl

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