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EECS 470

EECS 470. Cache and Memory Systems Lecture 14 Coverage: Chapter 5. Cache Modeling. Components: Storage modules module mem32x64 (clk, addr, data_in, rd_wrbar, data_out); input clk; // Clock input input [4:0] addr; // data address input [63:0] data_in; // write data

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EECS 470

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  1. EECS 470 Cache and Memory Systems Lecture 14 Coverage: Chapter 5

  2. Cache Modeling • Components: • Storage modules module mem32x64 (clk, addr, data_in, rd_wrbar, data_out); input clk; // Clock input input [4:0] addr; // data address input [63:0] data_in; // write data input rd_wrbar; // 1'b1 does a read, 1'b0 does a write output [63:0] data_out; // read data // All writes occur at the negative clock edge // All read data is available within 1 clock cycle endmodule

  3. Cache Modeling • Components: • Cache line overhead • Tag storage (1..n bits) • Valid bit (1 bit) • Dirty bit (0 or 1 bit) • Set overhead • Nothing for Direct mapped • LRU state machine for set associative (victim) • Internal Organization • Muxes, decoders, tag compare logic • External Interface • Command bus, data buses, clock, protocol, interaction with pipeline • 64-bit bus to processor, 64-bit bus to memory, blocking?

  4. Cache Modeling • LRU state logic • 2 lines is easy • Only two states (lines 0 is LRU; line 1 is LRU) • Single bit (set on access to line 0; reset on access to line 1) • 4 lines is tougher • How many states? • Enumerate them • L0, L1, L2, L3 • L0, L1, L3, L2 • … • L3, L2, L1, L0 • Build a state machine to recognize the state. • How do you update the state if L1 is referenced? • How is a victim cache different?

  5. Homework #4 2. (40 pts) Extend the Verisimple pipeline from HW3 5b (or 5a or Verisimple) to include split instruction and data caches. Both caches should be able to handle indeterminate memory latencies and interface to the unchanged memory provided with the pipeline. They only need to support 8-byte reads and writes. Both I-cache and D-Cache should be 4K direct-mapped with 32 byte lines. The D-cache also includes a 4-line victim cache (fully associative, LRU with 32 byte lines).

  6. Issues with DRAM • Density is good since they need only a single transistor. • They can lose the bit over time -> need for refresh • Refresh done by reading each row • If access occurs during refresh, access must wait (5% of time) • Memory must have signal saying when data is available

  7. An Alternate Approach • Split transaction bus protocol • Add more state to controller in memory to enable multiple independent accesses to memory chip. Use synchronous protocol so address does not need to be acked Access can be read/write for various sized data Memory will send signal when data is available (in order) Example: RAMBUS

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