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EECS 150 - Components and Design Techniques for Digital Systems Lec 07 – PLAs and FSMs 9/21-04

EECS 150 - Components and Design Techniques for Digital Systems Lec 07 – PLAs and FSMs 9/21-04. David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150.

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EECS 150 - Components and Design Techniques for Digital Systems Lec 07 – PLAs and FSMs 9/21-04

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  1. EECS 150 - Components and Design Techniques for Digital Systems Lec 07 – PLAs and FSMs9/21-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150 EECS150 F04 Culler

  2. Review: minimum sum-of-products expression from a Karnaugh map • Step 1: choose an element of the ON-set • Step 2: find "maximal" groupings of 1s and Xs adjacent to that element • consider top/bottom row, left/right column, and corner adjacencies • this forms prime implicants (number of elements always a power of 2) • Repeat Steps 1 and 2 to find all prime implicants • Step 3: revisit the 1s in the K-map • if covered by single prime implicant, it is essential, and participates in final cover • 1s covered by essential prime implicant do not need to be revisited • Step 4: if there remain 1s not covered by essential prime implicants • select the smallest number of prime implicants that cover the remaining 1s EECS150 F04 Culler

  3. Big Idea: boolean functions <> gates • 22^n boolean functions of n inputs • Each represented uniquely by a Truth Table • Describes the mapping of inputs to outputs • Each boolean function represented by many boolean expressions • Axioms establish equivalence • Transform expressions to optimize • Each boolean expression has many implementations in logic gates • Canonical: Sum of Products, Product of Sums • Minimal • K-maps as a systematic means of reducing Sum of Products • Any acyclic network of gates implements a boolean function EECS150 F04 Culler

  4. Outline • Programmable Logic to Implement Sum of Products • Designing with PLAs • Announcements • FSM Concept • Example: history sensitive computation • Example: Combo lock • Encodings and implementations EECS150 F04 Culler

  5. How to quickly implement SofPs? EECS150 F04 Culler

  6. One Answer: Xilinx 4000 CLB EECS150 F04 Culler

  7. Two 4-input functions, registered output EECS150 F04 Culler

  8. 5-input function, combinational output EECS150 F04 Culler

  9. Programmable Logic • Regular logic • Programmable Logic Arrays • Multiplexers/Decoders • ROMs • Field Programmable Gate Arrays (FPGAs) • Xilinx EECS150 F04 Culler

  10. • • • inputs ORarray ANDarray productterms outputs • • • Programmable Logic Arrays (PLAs) • Pre-fabricated building block of many AND/OR gates • Actually NOR or NAND • ”Personalized" by making or breaking connections among gates • Programmable array block diagram for sum of products form EECS150 F04 Culler

  11. product inputs outputs term A B C F0 F1 F2 F3AB 1 1 – 0 1 1 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1 reuse of terms Shared Product Terms F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A example: input side: personality matrix 1 = uncomplemented in term 0 = complemented in term – = does not participate output side: 1 = term connected to output 0 = no connection to output EECS150 F04 Culler

  12. Before Programming • All possible connections available before "programming" • In reality, all AND and OR gates are NANDs EECS150 F04 Culler

  13. B C A AB B'C AC' B'C' A F0 F1 F2 F3 After Programming • Unwanted connections are "blown" • Fuse (normally connected, break unwanted ones) • Anti-fuse (normally disconnected, make wanted connections) EECS150 F04 Culler

  14. A B C D AB A'B' CD' C'D AB+A'B' CD'+C'D Alternate Representation for High Fan-in Structures • Short-hand notation--don't have to draw all the wires • Signifies a connection is present and perpendicular signal is an input to gate notation for implementing F0 = A B + A' B' F1 = C D' + C' D EECS150 F04 Culler

  15. A B C A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC A B C F1 F2 F3 F4 F5 F6 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1 F1 F2 F3 F4 F5 F6 Programmable Logic Array Example • Multiple functions of A, B, C • F1 = A B C • F2 = A + B + C • F3 = A' B' C' • F4 = A' + B' + C' • F5 = A xor B xor C • F6 = A xnor B xnor C full decoder as for memory address bits stored in memory EECS150 F04 Culler

  16. A A A A 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X D D D D C C C C A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – – B B B B PLAs Design Example • BCD to Gray code converter K-map for W K-map for X minimized functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' K-map for Y K-map for Z EECS150 F04 Culler

  17. A B C D A BD BC BC' B C A'B'C'D BCD AD' BCD' W X Y Z PLAs Design Example (cont’d) • Code converter: programmed PLA minimized functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' not a particularly good candidate for PLA implementation since no terms are shared among outputs however, much more compact and regular implementation when compared with discrete AND and OR gates EECS150 F04 Culler

  18. A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – – PLAs Design Example (revisited) • BCD to Gray code converter A A 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X D D C C B B K-map for W K-map for X A A 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X minimized functions: W = X = Y = Z = D D C C B B K-map for Y K-map for Z EECS150 F04 Culler

  19. A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – – PLAs Design Example • BCD to Gray code converter A A 0 0 X 1 0 1 X 1 0 1 X X 0 1 X X 0 1 X 0 0 1 X 0 0 0 X X 0 0 X X D D C C B B K-map for W K-map for X BC’ A A 0 1 X 0 0 1 X 0 1 1 X X 1 1 X X 0 0 X 1 1 0 X 0 0 1 X X 1 0 X X minimized functions: W = X = Y = Z = D D C C B B K-map for Y K-map for Z EECS150 F04 Culler

  20. A A A A 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 1 1 1 0 0 A B C D D D D D A'B'C'D' A'BC'D ABCD AB'CD' AC' A'C B'D BD' A'B'D B'CD ABC BC'D' C C C C B B B B EQ NE LT GT PLA Second Design Example • Magnitude comparator K-map for EQ K-map for NE K-map for GT K-map for LT EECS150 F04 Culler

  21. Other Options • Muxes • DeMuxes • ROMs • LUTs • We will return to these later EECS150 F04 Culler

  22. Announcements • Reading: Katz 1.4.2 (again), 7.1-3, pp 174-186 • Mid term th 10/7 EECS150 F04 Culler

  23. Recall: What makes Digital Systems tick? Combinational Logic clk time EECS150 F04 Culler

  24. x reg[1]+17 1 ALU 3 MEM[r1+17] reg[1] 1. Instruction Fetch 5. Reg. Write 2. Register Read LW r3, 17(r1) 4. Memory 3. Execute 17 Recall 61C: Single-Cycle MIPS instruction memory PC registers Data memory +4 imm EECS150 F04 Culler

  25. x reg[1]+17 1 ALU 3 MEM[r1+17] reg[1] 1. Instruction Fetch 5. Reg. Write 2. Register Read LW r3, 17(r1) 4. Memory 3. Execute 17 Recall 61C: 5-cycle Datapath - pipeline IR instruction memory PC registers Data memory +4 imm EECS150 F04 Culler

  26. 000 001 011 010 110 111 101 100 Typical Controller: state state Next state Combinational Logic state Example: Gray Code Sequence state(t+1) = F ( state(t) ) EECS150 F04 Culler

  27. Output (t) = G( state(t) ) odd 0 1 1 0 1 0 0 1 101/0 100/1 001/1 000/0 010/1 110/0 111/1 011/0 Typical Controller: state + output state Next state Combinational Logic state state(t+1) = F ( state(t) ) EECS150 F04 Culler

  28. Output (t) = G( state(t) ) clr odd 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 1 x x x 0 0 0 clr=1 001/1 000/0 010/1 011/0 111/1 101/0 100/1 110/0 Typical Controller: state + output + input state Next state Input Combinational Logic state state(t+1) = F ( state(t), input (t) ) clr=0 clr=? EECS150 F04 Culler

  29. Two Kinds of FSMs • Moore Machine vs Mealy Machine Output (t) = G( state(t), Input ) Output (t) = G( state(t)) Input Input state Combinational Logic state state(t+1) = F ( state(t), input) state(t+1) = F ( state(t), input(t)) Input / Out State Input State / out EECS150 F04 Culler

  30. Parity Checker Example A string of bits has “even parity” if the number of 1’s in the string is even. • Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even and outputs a 1 if odd: • Can you guess a circuit that performs this function? EECS150 F04 Culler

  31. Formal Design Process • “State Transition Diagram” • circuit is in one of two states. • transition on each cycle with each new input, over exactly one arc (edge). • Output depends on which state the circuit is in. EECS150 F04 Culler

  32. present next state OUT IN state EVEN 0 0 EVEN EVEN 0 1 ODD ODD 1 0 ODD ODD 1 1 EVEN Formal Design Process • State Transition Table: • Invent a code to represent states: Let 0 = EVEN state, 1 = ODD state present state (ps) OUT IN next state (ns) 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 Derive logic equations from table (how?): OUT = PS NS = PS xor IN EECS150 F04 Culler

  33. ps ns Formal Design Process Logic equations from table: OUT = PS NS = PS xor IN • Circuit Diagram: • XOR gate for ns calculation • DFF to hold present state • no logic needed for output • Review of Design Steps: 1. Circuit functional specification 2. State Transition Diagram 3. Symbolic State Transition Table 4. Encoded State Transition Table 5. Derive Logic Equations 6. Circuit Diagram FFs for state CL for NS and OUT EECS150 F04 Culler

  34. Finite State Machines (FSMs) • FSM circuits are a type of sequential circuit: • output depends on present and past inputs • effect of past inputs is represented by the current state • Behavior is represented by State Transition Diagram: • traverse one edge per clock cycle. EECS150 F04 Culler

  35. FSM Implementation • FFs form state register • number of states  2number of flip-flops • CL (combinational logic) calculates next state and output • Remember: The FSM follows exactly one edge per cycle. EECS150 F04 Culler

  36. Another example • Door combination lock: • punch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset • inputs: sequence of input values, reset • outputs: door open/close • memory: must remember combination or always have it available as an input EECS150 F04 Culler

  37. Implementation in software integer combination_lock ( ) { integer v1, v2, v3; integer error = 0; static integer c[3] = 3, 4, 2; while (!new_value( )); v1 = read_value( ); if (v1 != c[1]) then error = 1; while (!new_value( )); v2 = read_value( ); if (v2 != c[2]) then error = 1; while (!new_value( )); v3 = read_value( ); if (v2 != c[3]) then error = 1; if (error == 1) then return(0); else return (1); } EECS150 F04 Culler

  38. value new reset clock open/closed Implementation as a sequential digital system • Encoding: • how many bits per input value? • how many values in sequence? • how do we know a new input value is entered? • how do we represent the states of the system? • Behavior: • clock wire tells us when it’s ok to look at inputs(i.e., they have settled after change) • sequential: sequence of values must be entered • sequential: remember if an error occurred • finite-state specification state EECS150 F04 Culler

  39. Sequential example: abstract control • Finite-state diagram • States: 5 states • represent point in execution of machine • each state has outputs • Transitions: 6 from state to state, 5 self transitions, 1 global • changes of state occur when clock says it’s ok • based on value of inputs • Inputs: reset, new, results of comparisons • Output: open/closed ERR closed C1!=value& new C2!=value& new C3!=value& new S1 S2 S3 OPEN reset closed closed closed open C1=value& new C2=value& new C3=value& new not new not new not new EECS150 F04 Culler

  40. data-path vs. control • Internal structure • data-path • storage for combination • comparators • control • finite-state machine controller • control for data-path • state changes controlled by clock new equal reset value C1 C2 C3 mux control multiplexer controller clock comparator datapath equal open/closed EECS150 F04 Culler

  41. ERR closed not equal& new not equal& new not equal& new S1 S2 S3 OPEN closed mux=C1 closed mux=C2 closed mux=C3 reset open equal& new equal& new equal& new not new not new not new Sequential example (cont’d):finite-state machine • Finite-state machine • refine state diagram to include internal structure EECS150 F04 Culler

  42. ERR closed next not equal& new not equal& new Symbolic states not equal& new reset new equal state state mux open/closed1 – – – S1 C1 closed0 0 – S1 S1 C1 closed0 1 0 S1 ERR – closed0 1 1 S1 S2 C2 closed0 0 – S2 S2 C2 closed0 1 0 S2 ERR – closed0 1 1 S2 S3 C3 closed0 0 – S3 S3 C3 closed0 1 0 S3 ERR – closed0 1 1 S3 OPEN – closed 0 – – OPEN OPEN – open0 – – ERR ERR – closed S1 S2 S3 OPEN closed mux=C1 closed mux=C2 closed mux=C3 reset open equal& new equal& new equal& new not new not new not new Sequential example (cont’d):finite-state machine • Finite-state machine • generate state table (much like a truth-table) Encoding? EECS150 F04 Culler

  43. binary One-hot hybrid Sequential example: encoding • Encode state table • state can be: S1, S2, S3, OPEN, or ERR • needs at least 3 bits to encode: 000, 001, 010, 011, 100 • and as many as 5: 00001, 00010, 00100, 01000, 10000 • choose 4 bits: 0001, 0010, 0100, 1000, 0000 • Encode outputs • output mux can be: C1, C2, or C3 • needs 2 to 3 bits to encode • choose 3 bits: 001, 010, 100 • output open/closed can be: open or closed • needs 1 or 2 bits to encode • choose 1 bits: 1, 0 EECS150 F04 Culler

  44. next reset new equal state state mux open/closed1 – – – 0001 001 0 0 0 – 0001 0001 001 00 1 0 0001 0000 – 00 1 1 0001 0010 010 0 0 0 – 0010 0010 010 00 1 0 0010 0000 – 00 1 1 0010 0100 100 0 0 0 – 0100 0100 100 00 1 0 0100 0000 – 00 1 1 0100 1000 – 1 0 – – 1000 1000 – 10 – – 0000 0000 – 0 Sequential example (cont’d):encoding • Encode state table • state can be: S1, S2, S3, OPEN, or ERR • choose 4 bits: 0001, 0010, 0100, 1000, 0000 • output mux can be: C1, C2, or C3 • choose 3 bits: 001, 010, 100 • output open/closed can be: open or closed • choose 1 bits: 1, 0 good choice of encoding! mux is identical to last 3 bits of next stateopen/closed isidentical to first bitof state EECS150 F04 Culler

  45. Sequential example (cont’d):controller implementation • Implementation of the controller special circuit element, called a register, for remembering inputs when told to by clock new equal reset mux control controller clock new equal reset open/closed mux control comb. logic clock state open/closed EECS150 F04 Culler

  46. Even Parity Checker Circuit: In General: FFs must be initialized for correct operation (only one 1) One-hot encoded FSM EECS150 F04 Culler

  47. Often PLAs FSM Implementation Notes • General FSM form: • All examples so far generate output based only on the present state: • Commonly called Moore Machine (If output functions include both present state and input then called a Mealy Machine) EECS150 F04 Culler

  48. Design hierarchy system control data-path coderegisters stateregisters combinationallogic multiplexer comparator register logic switchingnetworks EECS150 F04 Culler

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