Design and Implementation of VLSI Systems (EN0160) Lecture 32: Array Subsystems (DRAM/ROM)

1. Design and Implementation of VLSI Systems (EN0160) Lecture 32: Array Subsystems (DRAM/ROM) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. Last time Memory periphery (row/column circuitry) Core cell: SRAM cells This time (different core cells) DRAM cells ROM cells Non Volatile Read Write (NVRW) cells Lecture outline

3. WWL RWL write WWL M3 Vdd BL1 X M1 M2 X Vdd-Vt Cs RWL read BL2 BL1 Vdd-Vt BL2 V 3T DRAM cell • No constraints on device sizes (ratioless) • Reads are non-destructive • Value stored at node X when writing a “1” is VWWL - Vtn

4. WL write “1” read “1” WL X M1 X Vdd-Vt Cs CBL Vdd BL Vdd/2 BL sensing 1T DRAM Cell Write: Cs is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between CBL and Cs Read is destructive, so must refresh after read Leakage cause stored values to “disappear” → refresh periodically

5. The bit line is precharged to VDD/2

6. How DRAM cells are manufactured? Trench capacitor

7. rejects common mode noise DRAM subarray architectures sensitive to noise

8. Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0 ROMs

9. 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1’s in ROM Dot diagram NOR ROMs Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010 Looks like 6 4-input pseudo-nMOS NORs

10. V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] NAND ROM • All word lines high by default with exception of selected row • No transistor with the selected word -> bitline pulled down • Transistor with the selected word -> bitline remain high

11. Floating gate Gate Source Drain t ox t ox D + +_ n n p Substrate G Schematic symbol Device cross-section S Non Volatile Read/Write (NVRW) memories • Same architecture as ROM structures • A floating transistor gate is used • similar to traditional MOS, except that an extra polysilicon strip is inserted between the gate and channel • allow the threshold voltage to be progammable

12. 20 V 5 V 0 V 20 V 5 V 0 V - 10 V 5 V 2.5 V 5 V - S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V . T Floating gate transistor programming Floating gate is surrounded by an insulator material  traps the electrons Process is self-timing - Effectively increases Threshold voltage

13. Flash Electrically Erasable ROMs Control gate Floating gate erasure Thin tunneling oxide 1 1 n source n drain programming p- substrate To erase: ground the gate and apply a 12V at the source

14. Basic Operations in a NOR Flash Memory―Erase

15. Basic Operations in a NOR Flash Memory―Write

16. Basic Operations in a NOR Flash Memory―Read

17. So far, we covered Periphery ( row decoders / column circuitry) For the memory core: SRAM cells DRAM cells ROM NVWRM Summary