Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design

1. Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao1, Chenming Hu1, Xuejue Huang1, Andrew B. Kahng2, Sudhakar Muddu3, Dirk Stroobandt4, Dennis Sylvester5 1EECS Department, University of California, Berkeley 2Now with ECE and CS Department, University of California, San Diego 3Formerly with Silicon Graphics, Inc. 4ELIS Department, Ghent University, Belgium 5Now with EECS Department, University of Michigan, Ann Arbor

2. Outline • Introduction • Study implementation • Global interconnect optimization issues • Inductance effect • Repeater insertion • Via parasitics • Conclusions

3. Critical Path Delay Estimation Performance Prediction • Performance estimated from critical path analysis • Previous prediction assumes: • RC line model for interconnect delay • Switch factor bounded by {0,2} • Optimal repeater sizing and ideal placement • Design constraints excluded, such as noise margin, delay uncertainty and area cost • Via resistance from buffer insertion neglected • How valid are these assumptions?

4. Research Framework • GSRC Technology Extrapolation (GTX) Engine : http://vlsicad.cs.ucla.edu/GSRC/GTX • Allows users to flexibly capture and study the impact of alternative modeling choices and optimization constraints

5. Simulation Setup • Typical 0.18μm MOSFET technology • 15mm copper global interconnect, line thickness=1.3μm • Inverting buffers inserted

6. Vdd Vin Vout RC Vdd Vout RLC Line Inductance • In DSM regime, inductance is more important with • Increasing operation frequency • Lower line resistance • Larger global interconnect cross-sectional dimension • using Cu

7. Inductance Effect on Line Delay RC_Bakoglu • Line behavior is RLC dominant when b12-4b2<0, where b1=RsC+RsCL+RCL, b2=RsC2/6+RsRCCL/2+RC2/24+R2CCL/6+LC+LCL • Simple RC model underestimates line delay by more than 40% in RLC-dominated cases 225 RLC_Friedman 200 RLC_Kahng/Muddu 175 HSPICE 150 125 Interconnect Delay (ps) 100 75 RLC - dominated Case 50 25 3 4 5 6 7 8 9 10 Interconnect Length (mm)

8. Vin1 Cc SF*Cc Vin2 Switch Factor (SF) Effect • Previous models simply use switch factor bounded by {0,2} for further simulations • Detailed analysis predicts that the range of SF can be {-1,3}, depending on different transition time of inputs* *A.B. Kahng, S. Muddu, and E. Sarto, “On Switch Factor Based Analysis of Coupled RC Interconnects”, Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 79-84

9. Vdd/GND Lines Shielding Technology One Side Shielding (1S) Two Side Shielding (2S) No Shielding (NS) • Shielding is helpful to define the current return path for inductance coupling and to reduce crosstalk noise. But it increases area cost for signal lines • Cost function = Signal wire pitch x Repeater sizex Number of repeaters Signal Lines

10. 10 RC/SF=1 RC/SF=2 8 RC/SF=3 Constraints Optimized Cost within RLC/SF=1 6 RLC/SF=2 RLC/SF=3 4 2 NS 2S 1S Shielding Cost Optimization • Cost optimization constraints: line delay < 1ns; noise peak < 20% Vdd; transition time < 500ps; delay uncertainty < 15% • Ignoring inductance can overestimate cost function (>20%)

11. Critical Path Structure Wire and Repeater Sizing • For a line with fixed length, its width and spacing need to be well sized to optimize delay • Non-linear dependence of line delay on line length enables suitable buffer insertion to improve performance • Buffer scaled based on the loading it drives

12. Formula 2.2 2.2 RC, 1 pole RLC 2.0 2.0 1.8 1.8 1.6 1.6 1.4 1.4 Optimal Wire Width (μm) 1.2 1.2 1.0 1.0 0.8 0.8 Repeater size = 100 X min 0.6 0.6 0.4 0.4 0 2 4 6 8 10 Line Length (mm) Wire Size Optimization • RC formula for optimal line width:* • RC formula overestimatesoptimal width up to 30% from RLC model *J. Cong and D.Z. Pan, “Interconnect Estimation and Planning for Deep Submicron Designs”, Proc. DAC, 1999, pp. 507-510

13. 2.4 L = 2.14 mm segment 6 2.2 W=S=1.0 mm 2.0 W=S=0.5 mm 5 1.8 4 Critical Path Delay (ns) 1.6 Normalized Energy-Delay Product 1.4 3 1.2 2 1.0 0.8 1 Bakoglu optimal sizing 0 100 200 300 400 500 Repeater Size (X min size) Repeater Size Optimization • Bakoglu sizing: • Simple sizing expression overestimates optimal repeater size by 400%

14. Repeater Placement Uncertainty • Buffers are inserted to specific position to optimize delay • However, repeaters are clustered into blocks to minimize wire cost at high level design; or restricted by available locations • Parameter εcaptures this placement uncertainty Lseg ε·Lseg

15. SF = 1 1.4 1.8 SF = 2 1.7 SF = 3 1.3 1.6 1.5 1.2 Normalized Delay 1.4 Normalized Peak Noise 1.3 1.1 1.2 1.1 1.0 1.0 0.0 0.2 0.4 0.6 0.8 1.0 Repeater Placement Uncertainty (e) Impact of ε • Repeater placement uncertainty ε has a large impact on peak noise (up to >70%) but little impact on delay (<5%)

16. Normal Repeater Insertion Staggered Repeater Insertion Staggered Insertion of Repeaters • With inverting buffer, staggered repeater placement makes overall switch factor close to one* • Peak noise and delay uncertainty benefit from staggered insertion *A. B. Kahng, S. Muddu, and E. Sarto, “Tuning Strategies for Global Interconnects in High-Performance Deep Submicron IC’s”, VLSI Design 10(1), 1999, pp. 21-34

17. 1.1 0.40 Non-staggered 0.9 0.35 Staggered (%) 0.7 0.30 dd 0.5 0.25 /V 0.3 0.20 peak Delay Uncertainty Ratio 0.1 V 0.15 -0.1 0.10 -0.3 0.05 -0.5 0.00 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Interconnect Spacing (μm) Non-staggered vs. Staggered • Staggered insertion significantly reduces peak noise to 4-7 times smaller than that of normal non-staggered insertion and almost eliminates delay uncertainty SF=3

18. Via Parasitics • Repeaters are inserted into top-level of metal routes • But devices must be on the bottom substrate • Current Al technology uses W as via and WNx as barrier. Both have larger resistivity than Al

19. SF = -1 20 20 SF = 1 18 18 SF = 3 16 16 14 14 % Increase in path delay 12 12 10 10 8 8 6 6 20 40 60 80 100 120 140 160 Repeater Size (X min size) Via Resistance Effect • Total via stack resistance is 47Ω for 0.18μm Al technology (signal line resistance is about 40Ω/mm) • Ignoring via parasitic resistance can introduce 10-20% underestimation of delay • In the future: copper can be used as via and may significantly reduce such impact

20. Summary +: previous models underestimate; –: previous models overestimate; x: no obvious change;

21. Conclusions • Have quantified several large sources of error in standard models used for interconnect optimization • Line inductance, via resistance • Design techniques: shielding, repeater clustering and repeater staggering • Accurate analytical models are required for optimal line and repeater sizing, and for accurate estimation of interconnect resource requirements • GTX allows rapid development, validation of interconnect performance models and optimizations