An Introduction to BORPH

1. An Introduction to BORPH Hayden Kwok-Hay So University of Hong Kong Aug 2, 2008 CASPER Workshop II

2. Reconfigurable Computing for Everyone • Language • Design Environment • Applications • OS • System Integration Hardware Software • Language • Design Environment • Applications • OS • System Integration BORPH

3. BORPH • Berkeley Operating system for ReProgrammable Hardware • OS for reconfigurable computers • Treats reconfigurable hardware as computational resources • UNIX interface to HW designs • Familiar to both software and hardware engineers • Design language independent • Goal: Make FPGA-based reconfigurable computers easy to use

4. Master-Slave Relationship Conventional View of FPGA Systems User Process (SW) User Process (SW) User Process (SW) User Library pipe socket file IPC Software OS Kernel Device Driver Hardware Platform (Network, UART, HD…) Hardware FPGA “coprocessor”

5. Peer-to-Peer Relationship BORPH Kernel User Process (HW) User Process (HW) BORPH Layers User Process (SW) User Process (SW) User Process (SW) User Library pipe IPC socket Software file ioreg virtual file Device Driver Hardware Platform (Network, UART, HD…) Hardware User Library Hardware

6. Hardware process Hardware syscall interface Interacting with an FPGA ioreg virtual file interface Hardware file I/O SW SW SW User Library pipe IPC socket file Software ioreg BORPH Kernel Device Driver Hardware Platform (Network, UART, HD…) Hardware User Library Hardware HW HW Overview of BORPH Concepts

7. SW SW SW User Library pipe IPC socket file Software ioreg BORPH Kernel Device Driver Hardware Platform (Network, UART, HD…) Hardware User Library Hardware HW HW Hardware Process • An executing instance of a hardware design • SW: An executing instance of a program • Normal UNIX process • Has pid, check status with ps, kill, etc • Unit of management • Created when a BORPH Object File (BOF) file is exec-ed • Kernel selects and configure hardware region automatically

8. SW SW SW User Library pipe IPC socket file Software ioreg BORPH Kernel Device Driver Hardware Platform (Network, UART, HD…) Hardware User Library Hardware HW HW HW Processes I/O • Standard UNIX I/O mechanism • File I/O, pipe, signal • I/O managed by kernel • Similar to SW • Hide details from users • e.g. HW-SW, HW-HW UNIX file pipe • HW specific service • ioreg virtual file system Don’t ask “How do I … in HW”. Think: “What if it were SW?”

9. ioreg Virtual File System • Maps user defined hardware constructs as virtual files under the process’s /proc/<pid>/hw/ioreg/ directory • Single word register • Memory: On-chip + Off-chip • FIFO • Example: • /proc/123/hw/ioreg/COUNTERVAL • ioreg information embedded in the executing BOF file • read and write system calls translated to message packet by the kernel • Any UNIX program can communicate with hardware processes • Shell: echo 1 > /proc/123/hw/ioreg/enable • C: MEM_FILE = • fopen(“/proc/123/hw/ioreg/MyMemory”, “r”); • fread(swbuf, 1, MEM_SIZE, MEM_FILE); • Python, Java, etc…

10. Message Parsing cnten cntval counter 1 en val Example ./counter.bof & [1] 2458 ps PID TTY TIME CMD 2456 pts/4 00:00:00 bash 2458 pts/4 00:00:00 counter.bof 2507 pts/4 00:00:00 ps cat /proc/2458/hw/ioreg/cntval A3B498E0 cat /proc/2458/hw/ioreg/cntval B289E906 echo 0 > /proc/2458/hw/ioreg/cnten cat /proc/2458/hw/ioreg/cntval C102F34D kill -9 2458 [1]+ Killed counter.bof bash$ bash$ BORPH Kernel counter.bof bash$ HWR bash$ bash$ bash$ 0 bash$ bash$ Configured

11. Analog Frontend A/D Baseband Process Upper Layer Decode Resize Edge Detect Encode video.out video.in Hardware File I/O • Access to the general file system from hardware processes • Debug by printing • printf • Read test vectors, record output • SW/HW processes chained by file pipe bash$ receiver.bof < file.in > file.out bash$ decode video.in | resize | edgdet.bof | encode > video.out

12. Simulink-Based Design Flow • Simulink: A block based design environment on top of Matlab • Familiar to communication/ protocol designers • Cycle-accurate, bit-accurate simulation in Simulink • Single-button to implementation • Based on Xilinx System Generator • In-house library for BEE2 specific blocks • I/O • BORPH integration

13. System Insertion Block Instantiation Synthesis, Map, Place & Route Config Generation counter.bof From Simulink to BOF

14. User Design User Design User Design User Design SelectMap MGT Direct Conn Ethernet Current Implementation on BEE2 • BORPH on PowerPC of center control FPGA • 1 user FPGA programmed for each hardware process • Based on Linux 2.4.30 kernel • Software reuse • Debian root filesystem BORPH

15. SelectMap FIFO System Architecture on BEE2 Ethernet Controller On-Chip Memory ioreg User Design PLB-OPB Bridge PLB-OPB Bridge User FPGA Control FPGA PPC PPC ioreg Shared BRAM Memory Controller SelectMap Control DMA Cntrl Shared FIFO A iock bfsio • Bus mastering DMA controller on Control FPGA • Improve configuration and data transfer • Direct HW access to SelectMap FIFO on User FPGA • Improved File I/O speed

16. User Design MGT Direct Conn Gb Ethernet On to ROACH… • 1 AMCC PowerPC 440 EPx • 1 Xilinx V5 FPGA • BORPH runs on PPC • v2.0 • 1 hardware process at a time BORPH

17. BORPH v2.0 • Based on Linux 2.6.25 kernel • Future proof • Modular • Easy to port to different platforms • e.g. Implementing ioreg interface for a new platform requires only 6 functions. • Many ports planned: • Backport to BEE2 • PC Desktop with FPGA card

18. Summary • BORPH is here, ready to use • Free, open source • If you know Linux, you can use it • BORPH is extensible • Able to run on anything that runs Linux • BORPH is more than a way to do I/O • Covers all aspect of reconfigurable computing