Surviving the Silicon Pipeline

1. Surviving the Silicon Pipeline 2006. 11. 27

2. Silicon Cycle

3. Frequently encountered problems during chip design project • (Quality of Starter Package ; QoSP) How do I know I am working on a right product in a right way? • Is the specification justified in terms of target customers’ demand (request, delivery time), resource I have (money, man power, tools)? • (Timeliness of Handshaking ; HoS) How do I make sure I can move to the next stage? • (Overhead) How much overhead is acceptable for each DFX (X=V, M, T)? • (Self-Adjustment) How do I know when and how to make/change the decision (on product specification, design flow, job assignment)?

4. FEP’s in pipeline terms • Imbalance of resource among pipeline stages • Needs constant monitoring of stable job flow • In case of imbalance, pipeline stalls. • Some overloaded, while others idle. • Expensive resource conflicts/under-utilization • Needs augmentation by finer pipelining or more parallelism • Proper overhead and transfer timing • Excessive overhead -> Current stage takes too long. • Too little overhead -> Subsequent stage takes too long. • Needs to set up a strategy for bug population control throughout the pipeline • Wrong guys (tools, IP’s, spec., designs..) stay too long in the pipeline -> detect and kill early

5. What is Specification? • Most basically, it is Requirement. • Requirement in terms of • Functionality • Performance (speed) • Power consumption • Cost (NRE, manufacturing) • And … Delivery time

6. Essential Components of Specification • Requirement ; • Specification must clarify what are wanted. • Implementation Readiness ; • Specification must be implementable. If so, how easy? • Scenario for getting it through ; • Strategies for • Confirming its completeness • Finding/correcting design errors • Maximizing yield through manufacturing

7. Platform-Based Design • Combining two levels (1+2) ; • considering both ‘What are wanted?’ and ‘Are they implementable?’ • Middle-out, or dual negotiation approach ; A compromise between Top-Down and Bottom-Up • Target hit probability is nearly doubled. • Limited to a given range of applications • Traversal time, or design time is reduced by ½ compared either to TD or BU

8. Specification coverage expands • Depending on the scope of your interest • Barely working design (of a product) • A profitable product (DFM, DFY) • Series of products (derivatives) • Company (company image, investor relations, early market entry…)

9. Pipeline Loss =Loss of Value through the Pipeline • Specification error • Design error • Verification error • Manufacturing error • Testing error

10. Specification error • Specification error = 1-Ps, or 1-Qs • Ps=probability of specification to be correct • Qs=quality of specification • Cost of specification error = Cs • Cs= 1) cost of extra silicon area due to over-design 2)price lowering due to speed degradation

11. Design error • Logical error during horizontal translation • Conflict with specification due to vertical (Downward) implementation • Library mapping = logical equivalence accompanied by such physical constraints as timing, power, and area. • Open-loop design complemented by back-annotation (to be zero-in by iteration) • Ex ; 1) Physical layout (Placement & Routing) after logic synthesis, 2) Component-based design followed by physical interconnect

12. Verification error • Verification error = 1-Pv, or 1-Qv • Pv=probability of verification to be correct = 1-probability of design error go unnoticed • Qv=quality of verification • Verification efficiency = Qv/(1+Cv) • Cv = verification overhead, or additional cost due to DFV (design for verification)

13. Pitfalls in Specification • Over-specification/over-design ; miss market window. • Too-long term, too conservative design project ; components obsolete at launch time. ex) military design • Too many external IP’s with insufficient 2nd sources or little room for royalty negotiation

14. Give and Takes of each DFX • DFV (Design for Verification) ; Design time for design time, code size for number of iterations, intra computing effort for inter communication hassle • DFT (Design for Testing) ; Area for reputation, good chips rejected is a physical loss, while bad chips with latent bugs is a strategic loss (X-factor) • DFM (Design for Manufacturability) ; More NRE cost (tool cost, extra preprocessing step) for less unit cost • DFY (Design for Yield) ; more parametric extraction and simulation time for higher yield

15. Area, delivery time, reputation, cost, speed, power

16. World of pipelines Silicon pipeline

17. Pipeline matching (Ti,Pi,Ci) • Ti ; execution time of the i-th stage • Pi ; probability (or percentage, in case of manufacturing/testing) • of fault at the end of i-th stage • Ci ; cost of execution of the i-th stage • Pipeline matching • Time matching ; uniformize Ti • Risk matching ; uniformize penalty function = Pi Ci • ex. As (fab cost x risk) is excessive, a new stage called FPGA • prototyping has appeared to redistribute the penalty

18. Silicon Pipeline System House Design House Chip Foundry Test & Packaging

19. Summit Attack summit C4 C3 C2 C1 Base Camp

20. Rocket Science DFV DFM DFT payload (Mi,Ei) overhead

21. Overhead of DFX DFV DFM DFT

22. Effect of DFV & DFT ; more than just time saving! Fault population Without DFV & DFT Manu facture Design Verify Test With DFV & DFT

23. Cost penalty of False pass/reject Stage i Stage i-1 Right pass False pass(FP) pass Right reject False reject(FR) reject Cost Penalty = FP x alpha + FR

24. Cost penalty of False pass/reject Stage i Stage i-1 Right pass False pass(FP) pass Right reject False reject(FR) reject Cost Penalty = FP x alpha + FR

25. Fi-1 Fi Si,Gi Silicon Pipeline Efficiency=B/A B A Pi=Ri x Σ Ci Fi=Fi-1 Si + Gi Right pass False pass Fi ; fault population at the i-th stage Si ; fault suppression function at the i-th stage Gi ; fault generation function at the i-th stage pass Right reject False reject reject Pi ; Cost penalty of Reject at i-th stage

26. Conclusion ; Silicon Pipeline Modeling • Silicon Pipeline Modeling is useful tool because • It Maximizes silicon pipeline efficiency. • Proper early investment of time & area for early detect & cure of faults • It maximizes resource (designer time, silicon area, expensive equipment time) utilization (Minimize resource conflicts)