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An Approach to the Design of Analog Fuzzy Logic Controllers in CMOS Technologies:

LABORATOIRE DE MICROELECTRONIQUE BATIMENT MAXWELL B-1348 LOUVAIN-LA-NEUVE BELGIQUE. An Approach to the Design of Analog Fuzzy Logic Controllers in CMOS Technologies: Implementation, Test and Application Carlos Dualibe.

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An Approach to the Design of Analog Fuzzy Logic Controllers in CMOS Technologies:

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  1. LABORATOIRE DE MICROELECTRONIQUEBATIMENT MAXWELL B-1348 LOUVAIN-LA-NEUVE BELGIQUE An Approach to the Design of Analog Fuzzy Logic Controllers in CMOS Technologies: Implementation, Test and Application Carlos Dualibe UCL- June 2001

  2. FUZZY LOGIC: Formalism for codifying Human Reasoning within a Numerical Framework.FUZZY SYSTEM: Model-Free Universal Approximator. Structured Knowledge Base (“if-then” rules) Usefulness: To solve problems that are either difficult to tackle mathematically or where its use provides improved performances and/or simpler implementations. Engineering Applications : -Process and Environmental Control (examples) -Robotics and Automation -Automotive Industrial Applications -Signal and Image Processing -Power Electronics -………… UCL- June 2001

  3. Hardware Implementation Choices for Fuzzy Controllers Allocation of the applications in the space [Complexity ; Time Response] Allocation of hardware solutions in the space [Complexity ; Time Response] Intended Target Applications: Signal and Image Processing, Power Electronics UCL- June 2001

  4. Why Analog? • Fuzzy Processing is analog in ‘nature’. • Usual applications demand reduced accuracy. • Low Power and/or High Speed • Reduced Complexity: Small area – No need of A/D and D/A • to interface Sensors and Actuators • Ideal for Embedded Subsystems. • Main Goals of this Work • Comprehensive study of the Analogue Fuzzy Operators • Design and Test of Programmable Architectures for Analogue Fuzzy Controllers • Secondary Goal: • To undertake preliminary studies of an embedded Fuzzy Logic application • in the field of Signal Processing. UCL- June 2001

  5. Fuzzy Controller Architecture and Fuzzy Algorithms R1: • Building Blocks: • Membership Functions • T-Norms ; T-CoNorms • Consequents • Defuzzifiers R2: Suits optimal for Hardware Implementation ! Fuzzy Controller UCL- June 2001

  6. Membership Functions Circuits: -Trapezoidal Shapes Based on Triode Transconductors TYPE –I: Differential Regulated Cascode Triode Transconductor Transfer Curve: Slopegm CrossoverVk Circuit : M1, M2Triode Non-Symmetric Diff. Amp. DA1,DA2 (W/L)Md1 > (W/L)Md2 Vds Vds UCL- June 2001

  7. Membership Functions Circuits (2): TYPE –II: Single Regulated Cascode Triode Transconductor Transfer Curve: Slopegm KneeV2=Vk + n Vds/2 Circuit : M1Triode M2 Saturated Vds M2: Large size transistor aimed for setting a conduction threshold n = Subthreshold slope factor UCL- June 2001

  8. Membership Functions (3) : Four Independent Parameters  2 slopes (gm1, gm2); 2 Crossover (Vk1 , Vk2) Iout1 Iout2 gm2 gm1 Vk1 Vk2 Vin Io Io Complementary FMF (CFMF) Direct FMF UCL- June 2001

  9. Membership Functions Circuits (4): Comparison against saturated transconductor Analogue Programming: Electrically Tunable Slopes by setting Vds Discrete Programming: large slope range is optimally allowed by a set of (W/L)s: Small Slopes can be set by using small Vds rather than very long channel Transistors Increased Current Consumption (Differential Amplifiers at the Regulation loop) More sensible to Mismatch (Triode transistors Vds) Triode Saturated UCL- June 2001

  10. Membership Functions Circuits (6): Full Programmable Compact Fuzzy Partition (Based on [1]) SPICE simulation for a 7-label Circuit: Io= 10A, Vdd=5V SlopesVs1,…Vs4 - Crossover points  Vk1<Vk2…<Vk4 Reduced number of transconductors Reduced Current Consumption Cumulative mirroring errors and delay due to cascading [1] Willamosky B. et al, ANNIE’96 UCL- June 2001

  11. T-Norm and T-CoNorm circuits: General Requirements In1 T-Norm or T-CoNorm Out InN • Multiple inputs (N) • O(N) Complexity: Size and consumption proportional to N • Parallel Processing:  No cascade tree of binary operators • Inputs Transparency:  Same load at each input - Same input/output delay Circuits: - Improved Lazzaro’s WTA-MAXIMUM - Mixed-Mode O(N) MAXIMUM - O(N2) LTA-MINIMUM - O(N) LTA-MINIMUM UCL- June 2001

  12. T-Norm and T-CoNorm (1): Lazzaro’s WTA-MAXIMUM Improved Version Concept Systematic Errors: ~1.6% • N current-controlled voltage-sources ( M1, M2 ) ‘fighting’ in parallel • Propagation error  Early effect in M2 ( Mo) • Discrimination error:   Early effect in M2 -  inversion degree of M1 • Mismatch error:  VT and  of M2, Mo UCL- June 2001

  13. T-Norm and T-CoNorm (2): Lazzaro’s WTA-MAXIMUM Delay & Undershot Improvement! E I1=5A I2=pulse 3A to 7A - 100ns UCL- June 2001

  14. T-Norm and T-CoNorm (3): Mixed-Mode MAXIMUM Systematic Errors: ~2.3% • Set of N Source Followers ‘fighting’ in parallel • Propagation error:   Voff = offset of A • Discrimination error:   Ao = DC gain of A • Mismatch errors:  due to Voffmainly Distribution of Input Signals achievable in voltage-mode !! UCL- June 2001

  15. T-Norm and T-CoNorm (4): New O(N2) LTA-MINIMUM [2] 2-Input MINIMUM 2-Input LTA & MINIMUM Systematic Errors: ~3% • Parallel comparison between input currents -Vdd limits the number of inputs • Propagation error:  Due to the Early Effect in transistors Mp • Discrimination error :   with the impedance of internal nodes (i.e.: V2) • Mismatch errors:  Associated with mirrors Mn and Mp [2] Dualibe, Jespers, Verleysen, IEEE ISCAS’2001 UCL- June 2001

  16. T-Norm and T-CoNorm (5): New O(N) LTA-MINIMUM [3] Improved Version with current feedback Ii Mirror Concept • N current-controlled voltage sources (Cells-i) ‘fighting’ in parallel • Current feedback improves accuracy of the MINIMUM (~ enhanced Wilson mirror) • Systematic error (~0.4%) • Mismatch error: due to VT and  of M5, M6 [3] Donckers, Dualibe, Verleysen, IEEE ISCAS’2000 UCL- June 2001

  17. Defuzzifiers : Closed Loop Defuzzifiers Voltage mode Current mode • Complexity increases with the • number of rules • May need frequency compensation • due to feedback:  speed • FMF or T-Norms’ gain must be controlled • May need frequency compensation • due to feedback:  speed UCL- June 2001

  18. Defuzzifiers(2): Open Loop Defuzzifiers Divider Pseudo-Normalizer • Complexity may increase with the number of rules (i.e.:R1….Rm) • Only one extra mirror per rule to compute denominator UCL- June 2001

  19. Defuzzifiers(3): Open Loop Defuzzifier with Divider ‘Common Weighting’ strategy for digitally programmable singletons. • ‘n’ mirrors per singleton • Silicon surface and input capacitance of each singleton result much smaller than in the ‘local weighting’ approach (i.e.: (2n/n) times reduced) • Only one D/A- Can be optimized to get desired accuracy • Simplicity UCL- June 2001

  20. Defuzzifiers(4): Novel Two-Quadrant Analog Divider [4] • M1= M2=M3triode •  • Input Nodes Nd and Nn become resistive! • Thus: • Vout-Vbo= (Vb1-Vbo) (IN/ k ID) • Current/input voltage/output IDEAL! Nd Nn • Systematic errors: - Mainly due to mobility reduction in triode transistors M1, M2, M3. • - Gain error and offset can be neglected if cascoded PMOS mirrors are used (M7, M8, M9). • Mismatch errors: -For small current ID, strongly influence of mismatch of VT between transistors M4,M5,M6. UCL- June 2001 [4] Dualibe, Verleysen, Jespers, IEE Electronics Letters, 1998.

  21. Defuzzifiers(5): Two-Quadrant Analog Divider-Measurement (+) Measured (-) Calculated Relative errors vs. ID: 2 A < IN < 8A; 10A< ID <30A (Vout-Vbo) vs. IN: 0< IN <10A; 10A< ID <30A Non-Linearity: UCL- June 2001

  22. Defuzzifiers(6): Comparison Against other Dividers Wiegerink R., Kluwer A. P., 1993 • Inputs must be supplied at different nodes • at least twiceAdditional mirroring errors • NL = ~1% Huertas et al, Trans. Fuzzy Systems, 1996 • Need extra I-to-V converter • Differential currents inputs • NL = ~1% (only divider) Divider Current-to-voltage converter UCL- June 2001

  23. Defuzzifiers(7): Electrically Programmable Singletons New Electrically Tunable Linear Current-Mirror Spice Simulation: 1V<Vb2<1.5V Other Approach: Sasaki et al, 3th Int. Conf. On Industrial Fuzzy Control and Intelligent Systems 1993 UCL- June 2001

  24. Estimation of the global accuracy of the Controller Only One Fired Rule: 2% < Vout/Vout <3% Unrealistic! Divider Singletons +D/A Mirror Vout % UCL- June 2001

  25. Estimation of the global accuracy of the Controller(2) Two Fired Rules in a complementary way: 2.5% < Vout/Vout <3.5% Vout for: 0.1< 1 < 0.9 2=0.9 %: (+) Divider (o) CFMF+T-Norm+Io UCL- June 2001 25

  26. Programmable Fuzzy Architectures: General Guidelines • Standard CMOS Technologies Mixed Signal :  Analogue Processing + Digital Programming • Current-Mode vs. Voltage-Mode: Current ModeVoltage Mode • Analog Computation:…………. + - • Signal Routing…….:…………..- + • Chip external Interface:……….. - + • MIXED MODE • Building Blocks Interface: Avoid the use of extra V-to-I or I-to-V convertersImproves Delays and Accuracy. • Modularity:Share operators (i.e: Membership Functions Circuits, Common weighting) • Transistors Sizing: Large size Good MatchingPoor Integration Density (dedicated controllers) • Small size Poor MatchingGood Integration Density (programm. controllers) • Programmability can help to relax sizing requirements for a given accuracy! UCL- June 2001

  27. A 9-Rule 2-Input 1-Output Programmable Fuzzy Controller [6] • Zero-Order Controller-Fixed Number of Rules (Grid Partition) • Complementary MF Labels (Type II – Three per input) • T-Norm: Complemented Lazzaro’s MAXIMUM • Defuzzifier: ‘Common weighting’ • Discrete Programming of Antecedents and Consequents • Intended for embedded applications [6] Dualibe, Jespers, Verleysen, IEEE ISCAS’2000 UCL- June 2001

  28. 9-Rule Fuzzy Controller (1): Membership Function Programming Linear Resistor • Measured CFMF Type-II: • Io=10A ; Vdd=5V • Input Range: 1.5V<Vin<4.5V Half CFMF Type-II • Local setting of analog parameters • s0…..s3Slopes (2x4-bit) • p0….p4Knees (2x5-bit) UCL- June 2001

  29. 9-Rule Fuzzy Controller (2):Test Result RMSE _max Mean() 27mV (2.7%) 62mV (6.2 %) 35mV (3.5%) MEASURED TARGET Relative Error Surface Relative Error Distribution Settling time (90%): S.Signal: ~190ns L.Signal: ~450ns UCL- June 2001

  30. 9-Rule Fuzzy Controller (3):Comparison [KeSc93] [MaFr96] [GuPe96] [BaHu98] [VaVi99] [DuVe00] Complexity 9rules@2input 9rules@2input 13rules@3input 9rules@2input 16rules@2input 9rules@2input @1output @2output @1output @1output @1output @1output m m m m m m Technology 3 Bi - CMOS 0.7 CMOS 2.4 CMOS 2.4 C MOS 1 CMOS 2.4 CMOS Power no data 44mW@5V 550mW@10V 20mW@5V 8.6mW@5V 13.4mW@5V Consumption Input to Output no data 550ns 160ns 2000ns 471ns 450ns Delay s s Precision no data no data RMSE: 3.33% no data : 4% : 6.2% MAX MAX Interface cur rents@ voltages@ voltages@ voltages@ voltages@ voltages@ (inputs@outputs) currents voltages voltages voltages currents voltages 2 2 2 2 2 2 Area 13.75mm 1.9mm 16.2mm 1mm 1.6mm 4.5mm Programmability MF Knees: fixed on chip (6b) off chip on chip (6b) off chip on chip (5b) MF Slopes: fixed fixed on chip (4b) on chip (2b) fixed on chip (4b) Consequents: fixed on chip (6b) off chip on chip (4b) on chip (4b) on chip (5b) UCL- June 2001

  31. Application Example: Fuzzy Control of a DC/DC “Buck” Converter[9] PWM “duty cycle”: Dp, Di: Highly Nonlinear functions Small Steady-State Error and Fast Settling Time for RL Changes ([9] Franchi E. et al., IEEE JSSC, June 1998) UCL- June 2001

  32. Application Example(2): Fuzzy Control of a DC/DC “Buck” Converter[10] Optimal Control Surfaces DI: 1 Input-1 Output 4 Rules DP: 2 Inputs-1 Output 4 Rules ([10] Rashid M., Power Electronics-Circuits, Devices and Applications, Prentice Hall, 1993) UCL- June 2001

  33. A General-Purpose Programmable and Reconfigurable Fuzzy Controller N  5; Q  3; M  27; F  16 • CFMF type-II • Programmable MAXIMUM mixed mode O(N) • SWITCH MATRIX: ‘smartly’ wired UCL- June 2001

  34. General-Purpose Controller (2): First-Order Output Configuration Divider Consequent Rule-i Novel High-Input Impedance Voltage Mode Adder: DefuzzifiedValue UCL- June 2001

  35. General-Purpose Controller (3): Zero-Order Test Result Surface RMSE _max Mean() a) 80mV (4%) 180mV (9 %) 64mV (3.2%) b) 94mV (4.7%) 240mV (12 %) 75mV (3.75%) Rules Map Measured Surface Relative Errors a) b) Settling time (90%): S.Signal: 570ns L.Signal: 1100ns UCL- June 2001

  36. General-Purpose Controller (4): 4-rules First-Order Controller Test Result Measured CFMF Measured Surface ANFIS Fitting: A comparison • 1st-Order; 4-rules • 28 parameters • RMSE: 0.8% • Zero-Order; 4-rules • 20 parameters • RMSE: 2% • Zero-Order; 9-rules • 33 parameters • RMSE: 1.4% UCL- June 2001

  37. COMPARISON UCL- June 2001

  38. General Purpose Controller (6):Further Improvements Cox Early AVTo CMOS 2.4 50 A/V 10V/ 24mV  CMOS 0.8 100 A/V 10V/ 12mV  • Scaling to Modern Technologies: A) Analog Circuits: Silicon Area Same Current Same Vdd, VTo 2 2 -Same L (keep same Early) -W  W/2 ===>50% Area Reduction Mismatch B) Digital Circuits: theoretical scaling factor: (1/9). Let us assume (1/4.5). Total Area Reduction: 39.5mm2 == 13.6mm2 UCL- June 2001

  39. Time-Domain Signal Analysis Using Fuzzy Logic and its Application to Self-Adaptive Channel Equalization General Setup Built-in ‘Oscilloscope’: inferred Assertions could be used for adaptation,detection,testing, etc. UCL- June 2001

  40. Continuous-Time Self-Adaptive Equalization based on the Eye-Pattern [8]: System Architecture B) A) E(s) = (s-z) (s+z) Adaptive Equalizing System Control Surface related to the Eye Pattern • On-Chip Real-Time Scope:  SIGNAL 2D-FIGURE (EYE PATTERN) • Controller’s Decision Making : “Keep ACTUAL EYE within AREA TOLERANCE” • Controller’s Output:  EQUALIZER’S ZEROS PLACEMENT UCL- June 2001 [8] Dualibe, Jespers, Verleysen, IEEE ISCAS’2001

  41. Fuzzy Logic Controller : Rule Base and Input Partition Boosting must Decrease Boosting must Increase Area Tolerance • RULE BASE: 25-Rules controlling Equalizer Amplitude Boosting (5-labels per input) • Area Tolerance: immunity to NOISE, RINGING, PULSE SHAPE, ETC UCL- June 2001

  42. Architecture of the Fuzzy Controller • Zero-Order Sugeno :25 rules • Fuzzifiers: 5-Labels per input. • T-Norms: 2-input MINIMUM (O(N2) ) • Defuzzifier: Averaged Weighted Sum • Discrete Programming of singletons (5-bits) UCL- June 2001

  43. 5-Labels Fuzzy Partition Circuit Vin SPICE simulation for Io=10A • Chained differential pairs: low consuming, small area and compactness • Vk1<Vk2<…..<Vk4 fix the crossover points • Fixed slopes at mask level by transistors Ma size UCL- June 2001

  44. Fuzzy Controller Test Results Measured Target UCL- June 2001

  45. Fuzzy Controller: Improvement Vs R3 R2 R1 R4 R6 R7 R5 R8 R9 R11 R10 Vt • Use Tree Partition for the input space to minimize rules set  ONLY 11 Rules • Input Vs Compact 5-Label Fuzzy partition circuit • Input Vt Six individual Membership Functions UCL- June 2001

  46. Amplitude-Boosting Gm-C Filter Bi-Quad Filter: A) Amplitude Phase • gm1=gm3=gm5=gmmaxfix • gm2=gm4tunable up to gmmax • Symmetric Zeros at: Theoretical Frequency Response UCL- June 2001

  47. New Full Electrically Tunable Triode Transconductor [9] Transconductance: • Linear tuningIz • Phase error < 2° Transconductor: Divider: CMFB with adaptive Bias Io [10] Improved common-mode voltage stability upon tuning. CMFB [9] Dualibe, Jespers Verleysen IEEE ISCAS’2001 UCL- June 2001 [10] DeLima, Dualibe, IEEE ISCAS’2000

  48. Equalizing Filter Test Results Measured AC Response UCL- June 2001

  49. Cable Equalization (simulations) A1) A2) B1) B2) Kz evolution for L=120, 240, 360m Eye Pattern: before and after the equalizer Signals for L=360m Fs = 5Mb/s Cable: CAT5 UTP UCL- June 2001

  50. Adaptation Performance for Noisy Channels Kz Evolution during adaptation Our Approach Widrow [85] Noise: Mean=0 -Variance=0.03 UCL- June 2001

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