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otmb_top Top module ( otmb_top.v )

otmb_top Top module ( otmb_top.v ). Modules are building blocks of the firmware. The following slides show structure of the modules hierarchy of the OTMB firmware. clock_ctrl. ccb. Legend: - modules which call other modules inside

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otmb_top Top module ( otmb_top.v )

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  1. otmb_top Top module (otmb_top.v) Modules are building blocks of the firmware. The following slides show structure of the modules hierarchy of the OTMB firmware clock_ctrl ccb Legend: - modules which call other modules inside - modules which DO NOT call other modules alct xxx cfeb … yyy MXCFEB = 7 cfeb pattern_finder sequencer rpc • otmb_topmodule: • named otmb_virtex6 • defined in file otmb_top.v buffer_write_ctrl buffer_read_ctrl tmb odmb_device vme miniscope parity sync_error_ctrl

  2. clock_ctrl Virtex6 Clock PLLs (clock_ctrl.v) phaser DCM Digital phase shift State Machine (phaser.v) phaser … MXDPS = 9 2 ALCT + 7 DCFEB phaser • Ports description: • clock inputs • tmb_clock0, tmb_clock0d, tmb_clock1, alct_rxclock, • alct_rxclockd, mpc_clock, dcc_clock • clock outputs • clock (from tmb_clock0), clock_2x, clock_lac, clock_vme • phase delayed clock (output) • clock_alct_rxd, clock_alct_txd, clock_cfeb[i]_rxd • global reset (output) • this is only based on clock stability, not a command function • clock DCM lock status • phaser VME control/status • clock input buffers • 40MHz from QPLL • 125 MHz from xtal • 160 MHz from QPLL for GTX • Ports description: • clocks • DCM lock status • DCM digital phase shift • VME control/status

  3. ccb CCB signals (ccb.v) x_oneshot Digital One-Shot (x_oneshot.v) x_oneshot • Ports: • input d • input clock • output q • How it works: • Produces 1-clock wide pulse when dgoes high • Waits for d to go low before re-triggering … • 6 instances: • uvmecs • uvmeds • uvmess • ualct_ext • uclct_ext • uvmel1a x_oneshot ccb_lock • 2 instances: • uccb_lock0 • uccb_lock1 ccb_lock • Ports: • CCB I/O • VME Control • TMB signals transmitted to CCB • TTC Command Word • TMB signals received from CCB • Monitored DMB Signals • DMB Received • MPC GTL Received data • Level 1 Accept Ports from VME and Sequencer • Trigger Ports from VME • TTC Decoded Commands • CCB TTC lock status ccb_lock Monitors TTC PLL lock signals from CCB (ccb_lock.v) • Ports: • input clock - TMB main 40MHz clock • input lock - Lock signal from TTC • input reset - Reset FFs and counter • output lock_never - Lock never achieved • output lost_ever - Lock was lost at least once • output lost_cnt- Number of times lock has been lost

  4. How it works: • Demultiplexes80MHz ALCT signals 1:2 to 40MHz • Maps ALCT rxnn signal names alct ALCT 80MHz Receiver / Demultiplexer (alct..v) x_demux_ddr_alct_muonic ecc32_encoder • Ports description: • Clocks • Phase delayed clocks • Global reset clocks • ALCT • TTC Command • CCB • Sequencer • TMB • VME Control/Status • VME ALCT sync mode • VME ALCT Raw hits RAM • TMB Control • Trigger/Readout Counter • ALCT Event Counters • ALCT Structure Error Counters • Test Points srl16e_bbl … • 8 instances: • usyncpre1st • usyncpre2st • usyncdly1st • usyncdly2st • udlya1st • udlya2nd • udlyb1st • udlyb2nd srl16e_bbl ecc32_decoder crc22a x_oneshot • 2 instances: • uextinj • uextrig x_oneshot ecc16_encoder alct_lfsr_rng x_mux_ddr_alct_muonic

  5. cfeb Process 1 CFEB (cfeb.v) • How cfebworks: • Input: 8 DiStrips x 6 CSC Layers • Output: 6x32=192 triad decoder pulses cfeb_bit_check triad_decode • Ports description: • Clocks • Global reset • Injector • Raw Hits FIFO RAM • Hot Channel Mask • Bad CFEB rx bit detection • Triad Decoder • Status • SNAP12 optical receiver • Optical receiver status gtx_optical_rx gtx_comp_fiber_in GTX_RX_BUF_BYPASS GTX_RX_BUF_BYPASS_GTX GTX_RX_SYNC gtx_prbs_rx_c160 gtx_lfsr_r24_c160 srl16e_bbl

  6. How pattern_finder works: • Load global definitions • Power up, reset, and purge • Pipeline purge blanks pattern finder until pipes are cleared • Pipeline purge state machine • Local copy of number-planes-hit pretrigger threshold powers up with high threshold to block spurious patterns • Generate mask for marking adjacent cfeb as hit if nearby keys are over thresh • Set CSC orientation • CSC_TYPE_C: Normal ME1B reversed ME1A • Generate hs reversal map for ME1A • Assign Reversed ME1A cfebs • Assign Normal ME1B cfebs • CSC_TYPE_D: Normal ME1A reversed ME1B • Generate hs reversal map for ME1B • Assign Reversed ME1B cfebs • Assign Normal ME1A cfebs • Combine ME1A and ME1B into one 7-CFEB CSC • Layer-trigger mode • delay 1bx for FF • Sum number of layers hit into a binary pattern number • Delay 1bx more to coincide with pretrigger • Delay 4bx to latch in time with 1st and 2nd clct, need to FF these again to align • 1/2-Strip Pattern Finder (Finds number of hits in pattern templates for each key 1/2-strip) • Create hs arrays with 0s padded at left and right cscedges • Pad 0s beyond csc edges ME1A hs128-223, isolate it from ME1B • Pad 0s beyond csc edges ME1B hs0-127, isolate it from ME1A • Find pattern hits for each 1/2-strip key • Store Pattern Unit results • S0 latch: realign with main clock, legacy to maintain sequencer timing • pre-s0 latch signals for pre-trigger speed • Convert s0 pattern IDs and hits into sort-able pattern numbers, [6:4]=nhits, [3:0]=pattern id • Pre-Trigger Look-ahead (Set active FEB bit ASAP if any pattern is over threshold. It comes out before the priority encoder result) • Flag keys with pattern hits over threshold, use fast-out hit numbers before s0 latch • Flag keys with pattern hits over threshold, use fast-out hit numbers before s0 latch • Sets Reversed/Unreversed ME1B/ME1A • Output active FEB signal, and adjacent FEBs if hit is near board boundary pattern_finder Builds and applies patterns (pattern_finder.v) srl16e_bbl … • 9 = 7+2 instances: • udlya0 • udlya1 • udlya2 • udlyb0 • udlyb1 • udlyb2 • udlyb3 • upatbbl • ukeybbl srl16e_bbl pattern_unit • 2 instances: • upat_me1a • upat_me1b pattern_unit best_1of32 best_1of7 best_1of32_busy best_1of7_busy • Ports description: • Clocks • CFEB • CSC orientation • PreTrigger • 2nd CLCT separation RAM Ports • CLCT Pattern-finder results continued on next page

  7. How pattern_finder works (cont’d): • 1/2-Strip Priority Encoder (Select the 1st best pattern from 224 Key 1/2-Strips) • Best 7 of 224 1/2-strip patterns • Best 1 of 7 1/2-strip patterns • Latch final hs pattern data for 1st CLCT • Delay 1st CLCT to output at same time as 2nd CLCT • Mark key 1/2-strips near the 1st CLCT key as busy to exclude them from 2nd CLCT priority encoding • 1/2-Strip Priority Encoder (Find 2nd best of 224 patterns, excluding busy region around 1st best key) • Delay 1st CLCT pattern numbers to align in time with 1st CLCT busy keys • Best 7 of 224 1/2-strip patterns • Best 1 of 7 1/2-strip patterns • Latch final 2nd CLCT • Sum number of layers hit into a binary value (Virtex-6 Specific procedural function)

  8. sequencer Sequences event processing (sequencer.v) • How sequencer works: • Pretriggerson either pattern finder or external trigger. • Sequences event processing. • Controls Raw Hits RAMs • Outputs CLCTs to TMB • Records TMB match result • Outputs Raw Hits to DMB x_oneshot scope160 • 2 = 1+1 instances: • uinjpulse • uveto x_oneshot x_oneshot x_flashsm x_delay … • 7 instances: • uflashf0 • … • uflashf6 • 2 = 1+1 instances: • uinjdly • udly0 x_flashsm x_delay x_delay_os … • 5 instances: • udly1 • udly2 • udly3 • udly4 • udly5 x_delay_os srl16e_bbl • 2 = 1+1 instances: • usrldrift • usrl1a srl16e_bbl ramblock … • 9 instances: • uramblock0 • … • uramblock8 ramblock crc22a continued on next page srl16e_bit

  9. sequencerports description: • CCB • ALCT • External Triggers • External Trigger Enables • Trigger modifiers • External Trigger Delays • CLCT/RPC/RAT Pattern Injector • Status from CFEB • Pattern Finder PreTriggerPorts • Pattern Finder CLCT results • DMB • ALCT Status • CSC Orientation Ports • CLCT VME Configuration • RPC VME Configuration • CCB Status Signals • Scintillator Veto • Front Panel LEDs • On Board LEDs • Buffer Write Control • Fence buffer adr and data at head of queue • Buffer Read Control • Buffer Status • CFEB Sequencer Readout Control • CFEB Blockedbits Readout Control • RPC Sequencer Readout Control • CFEB Sequencer Frame • CFEB BlockedbitsFrame • RPC Sequencer Frame • CLCT Raw Hits RAM • TMB-Sequencer Pipelines • TMB LCT Match • MPC Status • TMB Status • Firmware Version • RPC/ALCT Scope • Scope • Miniscope • Mini Sequencer Readout Control • Trigger/Readout Counter Ports • Event Counter • Parity Errors • VME debug register latches

  10. How rpcworks: • Receives 80MHz data from RPC • Demultiplexes, stores in RAM, and sends data to TMB rpc RPC 80MHz Receiver / Demultiplexer (rpc.v) srl16e_bbl • 2 instances: • urpc0dly • urpc1dly • Ports description: • RAT Module Signals • RAT Control • RAT 3D3444 Delay Signals • RAT Serial Number • RPC Injector Ports • RPC Raw Hits Delay • Raw Hits FIFO RAM Ports • RPC Scope Ports • RPC Raw hits VME ReadbackPorts • RPC Hot Channel Mask Ports • RPC BxnOffset • Status srl16e_bbl

  11. buffer_write_ctrl Raw Hits RAM buffer address logic (buffer_write_ctrl.v) • buffer_write_ctrlports description: • CCB • CFEB Raw Hits FIFO RAM • CFEB VME Configuration • RPC VME Configuration • Fence Buffer Write Control • Fence buffer adr and data at head of queue • Sequencer Buffer Read Control • Sequencer Buffer Status fence_queue ramblock buffer_read_ctrl Controls CFEB and RPC Raw Hits, and Miniscope RAM Readout to Sequencer (buffer_read_ctrl.v) • buffer_write_ctrlports description: • CCB • CFEB Raw Hits FIFO RAM • RPC Raw Hits FIFO RAM • Miniscpe FIFO RAM • CFEB Raw Hits Data • CFEB blockedbitsData • RPC Raw hits Data • MiniscopeData • CFEB VME Configuration • RPC VME Configuration • Minisocpe VME Configuration • CFEB Sequencer Readout Control • CFEB Blockedbits Readout Control • RPC Sequencer Readout Control • Mini Sequencer Readout Control • CFEB Sequencer Frame Output • CFEB Blockedbits Frame Output • RPC Sequencer Frame Output • Mini Sequencer Frame Output srl16e_bbl … • 16 = 5+2+6+3 • instances: • usrlc0 • … • usrlc4 • usrlbcb0 • usrlbcb1 • usrlr0 • … • usrlr5 • usrlm0 • usrlm1 • usrlm2 srl16e_bbl

  12. How tmbworks: • Sends 80MHz data from ALCT and Sequencer to MPC • Outputs ALCT+CLCT match results for Sequencer header • Receives 80MHz MPC desision result, sends de-muxed to Sequencer tmb TMB 80MHz Receiver / Sender (tmb.v) srl16e_bbl … • 28 instances: • ualct0 • ualct1 • ualcte • uclct0 • uclct1 • uclctc • uclctf • utwadr • utwpush • utwavail • ulct0quality • ulct1quality • uinjalctbx0 • uinjclctbx0 • ualctbx0 • uclctbx0 • umpctxdly0 • umpctxdly1 • umwadr • umwpush • umavail • umwtrigm • umpcmux • umpcdemux • umradr • umrpush • umravail • umrtrigm srl16e_bbl • tmbports description: • CCB • ALCT • TMB-Sequencer Pipelines • Sequencer • MPC Status • MPC IOBs • VME Configuration • VME Status • MPC Injector • Status

  13. How odmb_deviceworks: • If ODMB mode is selected, this module generates the DMB_TX signals and provides other ODMB functionalities odmb_device provides ODMB functionalities (odmb_device.vhd) pulse_edge • Ports: • In TMB 40MHz clock • In VME 10MHz clock • In Global reset • In VME address • In VME data • In 1 if read, 0 if write • In Board selected • Out ODMB mode selected • Out ODMB data alct_otmb_data_gen eofgen • 2 instances: • ALCT_EOFGEN_PM • OTMB_EOFGEN_PM eofgen

  14. vme VME Interface (vme.v) alct_startup x_oneshot … • 6 instances: • uevc • ubcn • ubx0 • usnap • uperr • upfire vmesm x_oneshot jtagsm_new jtagsm_old ddd_tmb gtx_sysmon ddd_rat cylon1 cylon2 x_flashsm dsn_tmb • 2 instances: • udsn_tmb • udsn_mez dsn_tmb dsn_rat

  15. vmeports description: • Clock • Firmware Version • ODMB device • VME Bus Input Port Map • VME Bus Output Port Map • Loop-Back Control Port Map • User JTAG Port Map • PROM Port Map • 3D3444 • Clock Single Step Port Map • Hard Resets Port Map • Status: LED Port Map • Status: Power Supply Comparator Port Map • Status: Power Supply ADC Port Map • Status: Temperature ADC Port Map • Status: Digital Serial Numbers Port Map • Status: Clock DCM lock • Status: Configuration State • CCB Ports: Status/Configuration • CCB Ports: VME TTC Command • CCB TTC lock status • CCB Ports: Trigger Control • ALCT Ports: Trigger Control • ALCT Ports: Sequencer Control/Status • VME ALCT sync mode ports • ALCT Raw hits RAM Ports • DMB Ports: Monitored Backplane Signals • CFEB Ports: Injector Control • CFEB Triad Decoder Ports • CFEB PreTriggerPorts • CFEB Ports: Hot Channel Mask • Bad CFEB rx bit detection • Sequencer Ports: External Trigger Enables • Sequencer Ports: Trigger Modifiers • Sequencer Ports: External Trigger Delays • Sequencer Ports: CLCT/RPC/RAT Pattern Injector • Sequencer Ports: CLCT Processing • Sequencer Ports: Latched CLCTs + Status • Sequencer Ports: Raw Hits Ram • Sequencer Ports: Buffer Status • Sequence Ports: Board Status • Sequencer Ports: Scope • Sequencer Ports: Miniscope • TMB Ports: Configuration • TMB Ports: Status • TMB Ports: MPC Injector Control • RPC VME Configuration Ports • RPC Ports: RAT Control • RPC Ports: RAT 3D3444 Delay Signals • RPC Ports: Raw Hits Delay • RPC Ports: Injector • RPC Ports: Raw Hits RAM • RPC Ports: Hot Channel Mask • RPC Ports: BxnOffset • ALCT Trigger/Readout Counter Ports • ALCT Event Counters • TMB+CLCT Event Counters • Header Counters • ALCT Structure Error Counters • CSC Orientation Ports • Pattern Finder Ports • 2nd CLCT separation RAM Ports • Parity Errors • VME debug register latches • DDR Ports: Posneg • Phaser VME control/status ports • Interstagedelays • Sync error source enables • Sync error action enables • Sync error types latched for VME readout • Virtex-6 QPLL • Virtex-6 SNAP12 receiver serial interface • Virtex-6 GTX receiver • Virtex-6 GTX error counters

  16. How miniscopeworks: • Records pre-trigger + alct*clct matching waveforms • Uses CFEB|RPC fifo addressing • Reads out into DMB data stream miniscope (miniscope.v) • Ports description: • Clock • DMB Readout FIFO RAM Ports • Status parity Process Parity Errors (parity.v) • Ports description: • Clock • Parity inputs • Raw hits RAM control • Parity summary to sequencer and VME sync_err_ctrl Synchronization Error Control (sync_err_ctrl.v) • Ports description: • Clock • Sync error sources • Sync error source enables • Sync error action enables • Sync error types latched • Sync error actions

  17. otmb_top buffer_write_ctrl odmb_device sequencer rpc pattern_finder vme fence_queue clock_ctrl srl16e_bbl srl16e_bbl x_oneshot pulse_edge alct_startup ramblock cfeb phaser alct_otmb_data_gen x_delay pattern_unit vmesm cfeb_bit_check eofgen ccb best_1of32 x_delay_os jtagsm_new triad_decode x_oneshot best_1of7 srl16e_bbl jtagsm_old gtx_optical_rx ccb_lock best_1of32_busy ramblock ddd_tmb gtx_comp_fiber_in crc22a best_1of7_busy GTX_RX_BUF_BYPASS ddd_rat alct GTX_RX_BUF_BYPASS_GTX srl16e_bit cylon1 tmb buffer_read_ctrl x_demux_ddr_alct_muonic scope160 GTX_RX_SYNC cylon2 srl16e_bbl srl16e_bbl ecc32_encoder x_oneshot gtx_prbs_rx_c160 x_flashsm srl16e_bbl gtx_lfsr_r24_c160 x_flashsm dsn_tmb ecc32_decoder dsn_rat crc22a srl16e_bbl x_oneshot x_oneshot gtx_sysmon miniscope ecc16_encoder parity alct_lfsr_rng x_mux_ddr_alct_muonic sync_error_ctrl

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