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Computer Architecture: Intro Anatomy of a CPU… cont. J. Schmalzel S. Mandayam. CPU. MEM. I/O. Hierarchical View of EP and Digital Systems. Operating System HLLs. Computer Architecture. State Machines. Interface Method. Design Techniques. MSI Functions. Boolean Algebra. Gates. Dbus.
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Computer Architecture: Intro Anatomy of a CPU… cont. J. Schmalzel S. Mandayam
CPU MEM I/O Hierarchical View of EP and Digital Systems Operating System HLLs Computer Architecture State Machines Interface Method Design Techniques MSI Functions Boolean Algebra Gates
Dbus RW Register File DA AA Const MB MuxB Aout Dout FS Function Unit Status Din MD MuxD Simple Model Data Path (7-18) n-bit bus Signal BA Dbus
Instruction Word 3 3 3 1 5 1 1 DA AA BA MB FS MD RW
Iword, cont. RW to write back result AA, BA, DA: 3-bit selection field to select 1-of-8 registers RF MB to select source operand for B path FU FS to select operation MD to select source for register file load
Function Select Codes 00000 F=A 00001 F=A+1 00010 F=A+B 00011 F=A+B+1 00100 F=A+ ~B 00101 F= A+ ~B + 1 00110 F=A-1 00111 F=A 01000 F=A & B 01010 F=A | B 01100 F=AB 01110 F= ~A 10000 F=B 10100 F= sr B 11000 F= sl B
FU (ALU) Design Approaches • Complex combinatorial structure • Multiplexed discrete logical and arithmetic units • HDL model
Consider Implementation • Use organization of FS codes to partition system (use FS4 and FS3): • 00- Arithmetic • 01- Logical • 10, 11- Shift, Miscellaneous
Behavior of Model CPU Fragment • RTL: Register Transfer Language • A compact way to describe data path operations COND: DESTINATION SOURCE{ | OPERATION | SOURCE…,DESTINATION SOURCE |…} M1: R7 R15 ;Conditioned on M1 state, move contents of R15 to R7 T2: R1R2, R3R4 & R6
RTL Examples (Table 7-12) R1 R2 + ~R3 +1 R4 sl R6 R7 R7 + 1 R1 R0 + 2 Data out R3 R4 Data in R5 0