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Pipeline Synchronization

Pipeline Synchronization. A Unique and Successfully Implemented Approach to the Synchronization Problem Based on the article “Pipeline Synchronization” by Jakov N. Seizovic, 1994. Search for New Solutions. More and more sync operations per unit time:

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Pipeline Synchronization

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  1. Pipeline Synchronization A Unique and Successfully Implemented Approach to the Synchronization Problem Based on the article“Pipeline Synchronization” by Jakov N. Seizovic, 1994

  2. Search for New Solutions • More and more sync operations per unit time: • complex chipsmore inter-domain transitions • Higher freq  less settling time  smaller MTBF • Existing solutions no longer deliver required PoF • And if they can it is a matter of the next generation or two… • inter-domain interfaces are often long interconnects; need to solve both with one mechanism

  3. Current Solutions • Reviewed in previous lectures • Two-flop • Clock shifting/streching, predicitve • … • All treat sync as “one-shot” process, at end of which signal is either synced or not

  4. Pipeline Synchronization • Pipeline approach: control signals synced in stages, alongwith data flow • Each step of the pipeline “partially synchronizes” the signal, reducing it’s degree of asynchronicity. • More stages  less PoF: safety vs. latency tradeoff • Data is latched at each stage • Divide long interconnect into short segments • Deal with inter-bit skew

  5. Degree of Asynchronicity • Until now, signal was either synchronous or asynchronous • For sync in stages, let’s look at more information: • A signal’s arrival time in interval [0-T] as random variable with distribution function •  and degree of asynchronicity :

  6. Asynchronicity of Signals • For a time-window 0<Tw<T, Asynchronicity of a signal is defined as: • Intuitive meaning: when sampling within a window of Thold+Tsetup=Tw ,As is the lowest prob. of MS behavior that can be achieved.

  7. Insightful Examples • Synchronous: can make As = 0 if satisfy Thold+Tsetup< certain Tmax • Asynchronous: As = Tw/T • As = 1 corresponds to a “Malicious” signal: no matter where we sample, the signal always arrives within our time window

  8. Pipeline Synchronization • Building blocks • Stage-synchronizer based on one or two Mutual-Exclusion elements • FIFO element • Start with async elements (latch & latch-like) • Explore possible use of DFFs for both data & sync (ctrl) path • More appealing to sync. designers

  9. Outputs mutually exclusive : only one asserts at a given time Connect ‘clk’ and signal ‘R’ to inputs ‘A’ synced output, other output unused R1 A1 ME R0 A0 S clk R A An ME as a Synchronizer (I) clk X

  10. An ME as a Synchronizer (II) A is synced to clk

  11. An ME as a Synchronizer (III) Inverse the clk:A syncs to clk sync to posedge clk R1 A1 ME R A R0 A0

  12. ME Implementation • A latch with a MS filter • As inherent to any sync. decision h/w, ME has a MS-state. • If in MS-state, Ao does not assert until MS resolved • Next clk edge forces ME out of MS-state.

  13. Dual-edge Synchronizer • Want to use 2-phase protocol, better for long interconnects • Need to sync rise and fall of Ri->Ro • Use 2 MEs and another latch

  14. FIFO Element • Holds data in stage while ctrl is synced • 2-phase single-rail handshake • 2-phase more suited for long interconnects • Latch as mem. element • can also use DFF, appeal to sync. designers • Simple async ctrl (petrify) • More on implementation next time…

  15. f0 f1 Pipeline w/ Embedded Synchronizing Asynchronous Synchronous f0 f1 f0 S S S Ri Ro Ri Ro Ri Ro Di Do Di Do Di Do Ao Ai Ao Ao Ai Ai Taken from “Synchronization Ideas”, Charles E. Dike, Intel Corporation

  16. f0 S S S Likewise for Multi-Synchronous Domains Mult.-sync. domain B Mult.-sync. domain A f1 f0 S S Ri Ro Ri Ro Ri Ro Di Do Di Do Di Do S Ao Ai Ao Ao Ai Ai f0 f1 f0 Taken from “Synchronization Ideas”, Charles E. Dike, Intel Corporation

  17. Step-by-Step

  18. Long Interconnect:Pipeline Synchronizer • Last 3 stages in each direction contain synchronizers A clk Bclk ME ME ME REQ ME ME ME ACK half cycle distance A clk B clk Seizovic, “Pipeline Synchronization,” Async 1994 Kessels, Peeters, Kim, "Bridging Clock Domains by synchronizing the mice in the mousetrap", PATMOS, 2003

  19. Probability of Failure • Pipeline PoF as formally proven in article:-k(T/2-Toh)/τPk=P0*e • P0– PoF without any sync • k– # stages • t = T/2-Toh is the time each sync has Toh = synchronizer+FIFO delay • Recall prob. of exit MS is P(t) = exp(-t/τ) • Intuitively, each stage works alone during its allocated time (while clk is high, minus overhead). The contributions are combined.

  20. Future • At each stage, time for sync isT/2 –Toh. Insert logic in the pipeline • On data, no problem • On ctrl possible, Toh effectively grows  need more stages for same PoF • But pipeline would have added functionality • Can also contemplate insertion of ME-elements along existing pipelines in synchronous designs…

  21. Glancing Back • Need for better solution that also addresses long-interconnect issue • Asynchronicity (degree of) • Syncing in stages: pipeline • ME as a synchronizer • FIFO element • Pipeline Synchronizers

  22. Next Presentation • More on Pipeline Sync, … • “Bridging Clock Domains by Synchronizing the Mice in the Mousetrap” Kessels, Peeters, KimPhilips Research Laboratory, 2003

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