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FEDv1 Final Firmware Subtasks

FEDv1 Final Firmware Subtasks. 15th March 2004. System ACE. EPROM. VME FPGA. Ed->Saeed. DAC. Opto Rx. EPROM. Temp. ADC. System ACE. DAC. Opto Rx. VME Bus. Temp. ADC. VME. Clocks. I2C. Clocks. Serial Comms. Regs. Clocks. Serial Comms. Regs. Data. Input. Serial

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FEDv1 Final Firmware Subtasks

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  1. FEDv1 Final Firmware Subtasks 15th March 2004 System ACE EPROM VME FPGA Ed->Saeed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC VME Clocks I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Data Input Serial Comms VME LINK Spy Data Header Mode Header Mode Cluster Mode Input Ed->Saeed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Saeed To be Implemented Control S-LINK S-LINK Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2

  2. FEDv1 Final Firmware Subtasks 4th November 2003 System ACE EPROM VME FPGA Ed->Saeed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC VME Clocks I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Data Input Serial Comms VME LINK Spy Data Header Mode Header Mode Cluster Mode Input Ed->Saeed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Saeed To be Implemented Control S-LINK S-LINK Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2

  3. FEDv1 Final Firmware Subtasks 22nd August 2003 System ACE EPROM VME FPGA Ed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC Temp VME I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Input Serial Comms VME LINK Data Data Header Mode Header Mode Cluster Mode Input Ed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Ivan To be Implemented Control S-LINK S-LINK Clocks Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2

  4. FEDv1 Final Firmware Subtasks 23rd July 2003 System ACE EPROM VME FPGA Ed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC Temp VME I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Input Serial Comms VME LINK Data Data Header Mode Header Mode Cluster Mode Input Ed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Ivan To be Implemented Control S-LINK S-LINK Clocks Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2

  5. FEDv1 Final Firmware Subtasks 26th June 2003 System ACE EPROM VME FPGA Ed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC Temp VME I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Input Serial Comms VME LINK Data Data Header Mode Header Mode Cluster Mode Input Ed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Ivan To be Implemented Control S-LINK S-LINK Clocks Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2

  6. FEDv1 Final Firmware Subtasks 11th June 2003 System ACE EPROM VME FPGA Ed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC Temp VME I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Input Serial Comms VME LINK Data Data Header Mode Header Mode Cluster Mode Input Ed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Ivan To be Implemented Control S-LINK S-LINK Clocks Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2

  7. FEDv1 Final Firmware Subtasks 15th May 2003 System ACE EPROM VME FPGA Ed DAC Opto Rx EPROM Temp ADC System ACE DAC Opto Rx VME Bus Temp ADC Temp VME I2C Clocks Serial Comms Regs Clocks Serial Comms Regs Input Serial Comms VME LINK Data Data Header Mode Header Mode Cluster Mode Input Ed FIFOs DELAY FPGA x 3 x 8 Scope Mode Output BE FPGA Saeed Scope Mode Serial Comms Regs VME Link External Devices FE FPGA x 8 Ivan To be Implemented Control S-LINK S-LINK Clocks Headers Under Simulation Throttle TCS Input Under Test on FED QDR Write QDR Read TTC chanA TTCrx Data Readout Saeed, Ivan “Working” on FED Chan B QDRs Controls Ed, John FEDv2

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