VLSI Physical Design Automation

1. VLSI Physical Design Automation Lecture 2. Review of Device/VLSI/Algorithm Prof. David Pan dpan@ece.utexas.edu Office: ACES 5.434

2. Objective of this Lecture • To review the materials used in fabrication of VLSI devices. • To review the structure of devices and process involved in fabricating different types of VLSI circuits • To review the basic algorithm concepts • To level-set everyone so that we can get into serious Physical Design topics in the next lecture

3. Wafer, Die and Package

4. Fabrication Materials copper

5. Electron and Holes Silicon atom Free Electron +Ion Hole http://researchweb.watson.ibm.com/resources/press/strainedsilicon/ • Holes travel as do electrons • Material can be enriched in holes or electrons by introducing impurities • Holes in crystals can be enriched by embedding some boron atoms • Electrons in crystals can be enriched by embedding phosphorus atoms • Recent breakthroughs: strained silicon (IBM) to stretch silicon such that electrons experience less resistance and flow up to 70% faster

6. Carrier-depletion zone Electron rich Interface Hole rich Formation of a Diffused Junction Silicon dioxide insulator Mask Phosphorous Depletion zone Substrate ( a ) ( b ) ( c ) The Three Regions in a n-p Junction A maskis a specification of geometric shapes that need to be created on a certain layer. Masks are used to create a specific patterns of each material in a sequential manner and create a complex pattern of several layers

7. Source Gate Drain Channel ( a ) ( b ) Gate Source Drain Vg<Vt VgVt Vs Vd Vs Vd ( c ) A nMOS Transistor Enhancement Mode

8. Fabrication of VLSI Circuits 1. Create 2. Define 3. Etch Silicon wafers Material formation by deposition, diffusion or implantation Pattern definition by photolithography Etch 8 to 10 iterations

9. UV Radiation Silicon dioxide Photoresist (Negative ) Silicon Shadow of mask feature ( a ) ( b ) Hardened Photoresist Silicon dioxide etched where exposed ( c ) ( d ) Photoresist stripped ( e ) Photolithographic Process Photo mask with opaque feature

10. Crystal growth & wafer preparation Epitaxy Dielectric & polysilicon film deposition Oxidation Diffusion Ion implantation Lithography Etching Packaging Details of Fabrication Processes

11. Basic Design Rules 1. Size Rules 2. Separation Rules 3. Overlap Rules Basic nMOS Design Rules

12. Diffusion Poly Metal Incorrectly and Correctly Formed Channels Diffusion Channel Short Poly Incorrectly formed Correctly formed Size and Separation Rules

13. Overlap Rules for Contact cuts ( b ) ( a )

14. Layout of Basic Devices • nMOS Inverter • CMOS Inverter • nMOS NAND Gate • CMOS NAND Gate • nMOS NOR Gate • CMOS NOR Gate Complicated devices are constructed by using basic devices

15. A CMOS Inverter

16. A CMOS NAND Gate

17. A CMOS NOR Gate

18. Additional Fabrication Factors • Scaling • Parasitic Effects • Yield Statistics and Fabrication Costs • Delay Computation • Noise and Crosstalk • Power Dissipation

19. Mini Summary • The three types of materials are insulators, conductors and semiconductors • A VLSI chip consists of several layers of different materials on a silicon wafer. • Each layer is defined by a mask • VLSI fabrication process patterns each layer using a mask • Complex VLSI circuits can be developed using basic VLSI devices • Design rules must be followed to allow proper fabrication • Several factors such as scaling, parasitic effects, yield statistics and fabrication costs, delay computation, noise and crosstalk and power dissipation play a key role in fabrication of VLSI chips

20. Complexity of VLSI circuits Performance Size Cost Market time Different design styles Full custom Standard Cell Gate Array FPGA Cost, Flexibility, Performance Design Styles

21. Pad Metal Via Metal 2 Data Path I/O PLA ROM/RAM Random logic A/D Converter Full Custom Design Style

22. Cell Feedthrough VDD GND Metal 1 Metal 2 D C C B A C C D C D B C C C B Cell A Cell B Cell C Cell D Feedthrough cell Standard Cell Design Style

23. A C B C A B Gate Array Design Style VDD Metal1 Metal2 Structured ASICs (hot topics nowadays) are essentially gate array

24. FPGA Design Style

25. Field-Programmable Gate-Arrays (FPGAs) • Programmable logic • Programmable interconnects • Programmable inputs/outputs

26. Comparisons of Design Styles style * uneven height cells are also used

27. style full-custom standard cell gate array FPGA compact to moderate Area compact moderate large high to moderate Performance moderate low high Fabrication layers routing layers ALL ALL none Comparisons of Design Styles

28. Packaging Printed Circuit Board PCB Multi-Chip Module MCM Wafer Scale Integration WSI (SOC) Area Performance, cost The increasing complexity and density of the semiconductor devices are driving the development of more advanced VLSI packaging and interconnection approaches. Packaging Styles

29. History of VLSI Layout Tools

30. Now You Need Algorithms • To put devices/interconnects together into VLSI chips • Fundamental questions: How do you do it smartly? • Definition of algorithm in a board sense: A step-by-step procedure for solving a problem. Examples: • Cooking a dish • Making a phone call • Sorting a hand of cards • Definition for computational problem: A well-defined computational procedure that takes some value as input and produces some value as output

31. Example: Selection Sort • Input: An array of n numbers D[1]…D[n]. • Output: An array of n numbers E[1]…E[n] such that E[1] E[2] … E[n]. • Algorithm: 1. For i from 1 to n do 2. Select the largest remaining no. from D[1..n]. 3. Put that number into E[i].

32. Some Algorithm Design Techniques • Greedy • Divide and Conquer • Dynamic Programming • Network Flow • Mathematical Programming (e.g., linear programming, integer linear programming)

33. Reduction • Idea: If I can solve problem A, and if problem B can be transformed into an instance of problem A, then I can solve problem B by reducing problem B to problem A and then solve the corresponding problem A. • Example: • Problem A: Sorting • Problem B: Given n numbers, find the i-th largest numbers.

34. Analysis of Algorithm • There can be many different algorithms to solve the same problem. • Need some way to compare 2 algorithms. • Usually run time is the most important criterion used • Space (memory) usage is of less concern now • However, difficult to compare since algorithms may be implemented in different machines, use different languages, etc. • Also, run time is input-dependent. Which input to use? • Big-O notation is widely used for asymptotic analysis

35. Big-O Notation • Consider run time for the worst input => upper bound on run time. • Express run time as a function input size n. • Interested in the run time for large inputs. • Therefore, interested in the growth rate. • Ignore multiplicative constant. • Ignore lower order terms. • 3n2+6n+2.7 is O(n2). • n1.1+10000000000n is O(n1.1). • n1.1 is also O(n2), but to be more precise, it is O(n1.1)

36. Effect of Multiplicative Constant n2 10n

37. Growth Rates of some Functions Polynomial Functions Exponential Functions

38. Problem of Exponential Function • Consider 2n, value doubled when n is increased by 1. • If you borrow $10 from a credit card with APR 18%, after 40 yrs, you will own $12700!

39. NP-Complete • The class NP-Complete is the set of problems which we believe there is no polynomial time algorithms. • Therefore, it is a class of hard problems. • NP-Hard is another class of problems containing the class NP-Complete. • If we know a problem is in NP-Complete or NP-Hard, there is no hope to solve it efficiently.

40. I can't find an efficient algorithm, I guess I'm just too dumb. I can't find an efficient algorithm, but neither can all these famous people. NP-Complete • I can't find an efficient algorithm, because no such algorithm is possible. Source: Computers and Intractibility by Garey and Johnson

41. Solution Type of Algorithms • Polynomial time algorithms • Exponential time algorithms • Special case algorithms • Approximate algorithms • Heuristic algorithms

42. Before Next Class • Refresh your Algorithms: • C. J. Alpert, D. P. Mehta, S. S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, Auerbach Publications, 2008 • T. H. Cormen, C. E. Leiserson, R. L. Rivest, C. Stein Introduction to Algorithms, MIT Press, 2009 (3rd edition) • Circuit partitioning in the next class