第 5 章 时序逻辑电路的分析与设计

1. 第5章时序逻辑电路的分析与设计

2. Chapter 5. 本章任务 • 1.学习时序逻辑电路的分析方法； • ２学习时序逻辑电路的设计方法； • ３学习中规模集成电路的应用；计数器，　 • 寄存器，移位寄存器,顺序脉冲发生器等;

3. Definition of sequential Logical circuits • 时序逻辑电路是一种在任何时刻的输出, 不仅取决于该时刻电路的输入,而且与电路过去的输入有关的逻辑电路.因此时序逻辑电路必须具有存储功能.

4. 时序逻辑电路的特点 • 1.除了有组合逻辑电路以外,还有存储电路, • (由F.F.组成)具有记忆过去输入信号的能 • 力; • 2.存储电路的状态反馈到输入端与输入信号共同决定其组合电路部分的输出.

5. Sec.5.1 引言 J-K F.F. Applications: 1 1 1 The nonoverlapping clock

6. D-F.F. J-K F.F.

7. 图5.1.2 时序逻辑电路的结构框图 返回

8. 时序逻辑电路的结构框图 Combination Logic Xi Yk Memory Logic WL Zm

9. Sequence Logical circuit described Method: • (1)output equation: • Y(tn) = F [x(tn), w(tn)] • (2)Driving equation: • w(tn+1)=H[Z (tn),W (tn) ] • (3)state equation: • z(tn) =G[x(tn), w(tn)]

10. Sequence Logical circuit Discrete form • (1)output equation: • Y = F [x, w] • (2)Driving equation: • w =H[Z ,W ] • (3)state equation: • z =G[x, w]

11. 时序逻辑电路的结构框图 wL Comb. Logic Zm Memory Logic Qn Xi Yk

12. 1.Mealy type state machine structure Next State Logic- F STATE Memory Output Logic- G excitation input Current state Output clk Clk signal Clocked synchronous state machine structure--Mealy type

13. Mealy type state machine function described Method: • Next state =F ( current state, inputs); • Output =G (current state, inputs);

14. 2.Moore type state machine structure Next State Logic- F STATE Memory Output Logic- G excitation input Current state Output clk Clk signal

15. Moore type state machine function described Method: • Output =G (current state, inputs);

16. The Mealy machine with pipelined outputs Next State Logic- F STATE Memory Output Logic- G Output Pipeline Memory excitation Pipe-line output input Current state clk clk Clk signal

17. 时序逻辑电路分析的目的: • The goal of sequential circuit analysis is: • to determine① the next state and • ② output function so that • ③ the behavior of a circuit can be • predicted.

18. Analysis Steps: • The analysis of a clocked synchronous state machine has three steps: • (1)Determine the next-state and output function F and G. • (2)Use F and G to construct a state/output table that • completely specifies the next state and output of the • circuit for every possible combination of current state • and input. • (3)(Optioned)Draw a state diagram that presents the • information from the previous step in graphical form.

19. Sequence circuit Analysis Steps: • 1.由给定的时序电路写出: • ①各F.F.含有时钟意义的特性方程; • ②激励方程(或驱动方程)即F.F.驱动信号表达式; • ③电路的输出方程. • 2.将各驱动方程代入对应F.F.的特性方程,求各F.F.的状态方程;并标明时钟条件,从而得到整个时序电路的状态方程组; • 3.由状态方程和输出方程得出该电路的状态转换真值表并检查电路能否自启动; • 4.根据状态转换真值表画出状态转换图和时序图; • 5.分析电路的功能. 花硬.P.1

20. Analysis of state machines with D-f.f. En F Input Output CLK State memory Output logic G Next state logic

21. State diagram corresponding to the state machine Max=0 En=1 En=1 En=1 En=1 A B En=1 En=1 Max=0 (F) Max=1 D C En=1 Max=0

22. Redrawn Logic diagram for a clocked synchronous state machine F Input Digital-2,p.87

23. Moore type state machine En=0 En=0 En=1 A B En=1 En=1 C D F=1 En=1 En=0 En=0

24. Synchronous Moore type 例1. clk 花硬,p.43

25. 例1. Timing waveform Q0 Q1 B

26. 例2. Synchronous Moore type 返回

27. 图5.2.2 图5.2.1电路的状态转换图 返回

28. 图5.2.3 图5.2.1电路的时序图 返回

29. 例3.Mealy type synchronous 花硬.P.49 返回

30. 图5.2.5 图5.2.4电路的状态转换图 返回

31. Analysis Method of Asynchronous Sequence circuit : • The special problems of Asynchronous Sequence circuit : • (1)异步时序电路中,F.F.时钟不是全部接于同一CLK脉冲源,因此电路的状态方程必须将每个F.F.的时钟信号作为一个变量写入; • (2)此状态方程所表示的逻辑功能只有在它的CLK输入触发信号到来时才起作用,并且只有F.F.边沿到来时状态方程 • 才成立,这决不是一个CLK变量与其它变量相与的逻辑关系. 花硬,P.40

32. The analysis method of asynchronoussequential circuits • The difference of asynchronous & synchronous: • 1.There are more than one CLK signals from the configuration • of circuit, or using the output of previous F.F. as a CLK • signal for the last F.F. • 2.

33. Moore type: Asynchronous sequential circuit F.F.2 F.F.1 F.F.3 花硬.P.54

34. The true table of state transition 态序NO. Q3 Q2 Q1 CP3=CP CP2=Q1 CP1=CP • 0 0 0 0 0 0 0 • 1 0 0 1 • 2 0 1 0 • 3 0 1 1 • 4 1 0 0 • 5 0 0 0 0

35. state transition DIAGRAM 001 010 100 000 011

36. Example4. Asynchronous Moore type:

37. Moore type: Asynchronous sequential circuit F.F.2 F.F.1 F.F.3 花硬.P.54

38. 图5.2.6 例5.2.4的异步时序逻辑电路

39. Example4. Asynchronous Moore type:

40. Shift Registers • Categorized: • 1.Serial In/Serial out shift register • 2. Serial In/parallel out shift register • 3. parallel In/Serial out shift register • 4. parallel In/parallel out shift register • 5.Bidirectional shift register • 6. shift register applications

41. 图5. 3.2 74LS175的逻辑图

42. 图5. 3.4 用D触发器构成的移位寄存器 Digital.p.26 返回

43. 图5. 3.5 图5.3.4电路的电压波形 返回

44. IC shift Registers 7495 Mode control s.In. cp1 cp2 D.E.p.379

45. 4-bit Bidirectional shift Register-74LS194 R/ L 花硬.p.125

46. 74194功能表 Rd’ S1 S0 工作状态 0 x x set 0 0 0 保持 1 0 1 右移 1 0 左移 1 1 1 并行输入 74LS194 4-bit bidirectional shift Register

47. 74LS194 application

48. The counter • 1.The counter overview: • To defined: • Counter: • Flip-Flops can be connected together to perform counting operated .Such a group of Flip-flops is a counter. • Modulus: • The number of flip-flops used and the way in which they are connected determine the number of states (called the modulus) and also Specific sequence of states that the counter goes through during each complete cycle.

49. 2.Counter categorized: • Counter are classified into two board categories according to two way they are clocked: • (1).Asynchronous counter: • Commonly called ripple counter, the first F.F. is clocked by the external clock pulse and then each successive F.F. is clocked by the output of the preceding F.F. • (2).Synchronous counter: • The clock input is connected to all of the F.F. so that they are clocked simultaneously. • Within each of these two categories, counter are classified primarily by the type of sequence, the number of states, or the number of F.F. in the counter.

50. 3.SPECIFIC DEVICES • 1.74LS93 4-bit binary counter • 274LS160 Synchronous decade add counter • 3.74LS161 4 bit Synchronous binary counter • 4.74LS163 4-bit binary counter, synchronous Reset • 5.74LS190 signal clock Synchronous decade up/down • counter • 6.74LS191 modulus 16 up/down counter • 7.74LS193 double clock Synchronous 16 up/down • counter • 8.74LS290 Decade Counter (2-5-10 asynchronous • counter)