Digital Integrated Circuits A Design Perspective

1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002

2. Chapter Overview • Memory Classification • Memory Architectures • The Memory Core • Periphery • Reliability • Case Studies

3. Semiconductor Memory Classification Non-Volatile Read-WriteMemory Read-Write Memory Read-Only Memory Random Non-Random EPROM Mask-Programmed Access Access 2 E PROM Programmable (PROM) FLASH FIFO SRAM LIFO DRAM Shift Register CAM

4. Memory Timing: Definitions Read-access is from read request time to the time data is available on the output Write-access is from the write request to the final writing of the input data to the memory

5. Decoder reduces the number of selected signals K = log N 2 Memory Architecture: Decoders M bits M bits S S 0 0 Word 0 Word 0 S 1 Word 1 Word 1 A 0 S Storage Storage 2 Word 2 Word 2 A cell cell 1 N words Decoder A K 1 2 S N 2 - 2 Word N 2 Word N 2 2 S N 1 2 - Word N 1 Word N 1 2 K log N = 2 Input-Output Input-Output ( M bits) ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals

6. Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word

7. Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

8. Block Diagram of 4 Mbit SRAM X – row address Y – column address Z – block address Clock -address -address Z X generator buffer buffer Predecoder and block selector Bit line load Block 1 128 K Array Block 0 Global row decoder Subglobal row decoder Subglobal row decoder Block 31 Block 30 Transfer gate Local row decoder Column decoder Sense amplifier and write driver CS, WE I/O x1/x4 -address -address Y X buffer buffer controller buffer buffer [Hirose90]

9. Contents-Addressable Memory Data (64 bits) Every row that satisfies the validity check (matches the mask bits) will activate the validity bits I/O Buffers Comparand Data pattern to be matched Commands Mask Priority encoder passes Only the valid rows and selects the one with the highest address in case of the multiple matches CAM Array ProrityEncoder Address Decoder R/W Address (9 bits) Control Logic 9 2 words 64 bits

10. DRAM Timing SRAM Timing Self-timed Multiplexed Addressing Memory Timing: Approaches Multiplexed addressing Smaller number of pins needed since row and column addresses are sent sequentially Strobe signals RAS and CAS are used to read them Complete addressing Complete address is presented at once with sensing circuits to detect transitions on the address buss

11. BL BL BL VDD WL WL WL 1 BL BL BL WL WL WL 0 GND Diode ROM MOS ROM 1 MOS ROM 2 Read-Only Memory Cells Bit line (BL) is resistively clamped to the ground, so its default value is 0 Diode disadvantage – no electrical isolation between bit and word lines BL is resistively clamped to VDD, so its default value is 1

12. MOS OR ROM BL [0] BL [1] BL [2] BL [3] WL [0] V DD WL [1] WL [2] V DD WL [3] V bias Pull-down loads

13. MOS NOR ROM V DD Pull-up devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]

14. MOS NOR ROM Layout Cell (9.5l x 7l) • Programming using the • Active Layer Only • diffusion is added to • create transistors GND Polysilicon GND Metal1 Diffusion Metal1 on Diffusion VDD VDD VDD VDD Connected to VDD through pMOS

15. MOS NOR ROM Layout Cell (11l x 7l) GND • Programming using • the Contact Layer Only • contacts are added • to create transistors Polysilicon Metal1 GND Diffusion Metal1 on Diffusion VDD VDD VDD VDD Connected to VDD through pMOS

16. MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] WL [1] WL [2] WL [3] All word lines high by default with exception of selected row

17. No horizontal contact to GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM MOS NAND ROM Layout Cell (8l x 7l) Programming using the Metal-1 Layer Only Polysilicon Diffusion Metal1 on Diffusion Add metal to eliminate transistor (short circuit)

18. NAND ROM Layout Cell (5l x 6l) Programming using Implants Only Polysilicon Threshold-alteringimplant Implant switches transistor on permanently thus eliminating it in ROM this results in a very small layout area (2 times smaller than NOR cell) Metal1 on Diffusion

19. V DD BL r word WL C bit c word Equivalent Transient Model for MOS NOR ROM Model for NOR ROM • Word line parasitics • Wire capacitance and gate capacitance • Wire resistance (polysilicon) • Bit line parasitics • Resistance not dominant (metal) • Drain and Gate-Drain capacitance

20. Equivalent Transient Model for MOS NAND ROM V DD Model for NAND ROM BL C L r bit c bit r word WL c word • Word line parasitics • Similar to NOR ROM • Bit line parasitics • Resistance of cascaded transistors dominates • Drain/Source and complete gate capacitance

21. Decreasing Word Line Delay

22. Precharged MOS NOR ROM V f DD pre Precharge devices WL [0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

23. D G S Non-Volatile MemoriesThe Floating-gate Avalanche injection MOS transistor (FAMOS) Floating gate Gate Source Drain t ox t ox + +_ n n p Substrate Schematic symbol Device cross-section

24. 20 V 0 V 5 V 20 V 0 V 5 V 10 V 5 V 5 V 2.5 V - - S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V . T Floating-Gate Transistor Programming Hot electrons go through the oxide and are trapped reducing floating gate voltage Typically new threshold is around 7 V so 5 V supply is not sufficient to turn transistor on, so the device is disabled

25. A “Programmable-Threshold” Transistor Shifted threshold effectively switches transistor off permanently Shift in the threshold depends on the charge injected onto the floating gate Injected charges are well insulated by silicon dioxide and can stay there with power off for many years. Floating gate used in almost all nonvolatile memories (EPROM, EEPROM, Flash)

26. Erasable-Programmable Read-Only Memory (EPROM) • EPROM is erased by shining ultraviolet light through a transparent package window • UV makes the oxide slightly conductive by generation of electron-hole pairs • The erasure process is slow (seconds to minutes) • Programming takes 5-10 msec • Erasing can be repeated up to a thousand times • Threshold is difficult to control after many erasures so special on-chip circuitry is required to control it • High current required during programming

27. Floating Gate Tunneling Oxide FLOTOX Transistor EEPROM Gate Floating gate I Drain Source V 20 – 30 nm -10 V GD 10 V 1 1 n n Substrate p 10 nm Fowler-Nordheim tunneling I-V characteristic FLOTOX transistor Smaller voltage is required to program and programming is reversible by changing the voltage sign

28. V DD EEPROM Cell BL • Absolute threshold control • is hard • Programmed transistor might • be in depletion mode hard to • turn off by word-line signal • 2 transistor cell • Design is larger than EPROM device • Thin oxide is hard to make • Erase-program can be repeated 105 times WL

29. Control gate Floating gate Erasure 12 V on source Thin tunneling oxide ~10 nm + + n source n drain Programming 12 V on gate p- substrate Flash EEPROM • Flash EPROM combines density of EPROM with versatility of EEPROM • Programming performed by avalanche hot-electron injection (fast 1-10msec) • Erasure of the complete chip is done using tunneling (careful control >100ms) • No extra access transistor needed

30. Cross-sections of NVM cells Flash EPROM Courtesy Intel

31. Basic Operations in a NOR Flash Memory―Erase All transistors erased Read back and repeat if erase is still needed

32. Basic Operations in a NOR Flash Memory―Write Programming requires 12V ant the gate and 6V at the drain with 0V source

33. Basic Operations in a NOR Flash Memory―Read • In read operation the programmed • transistor stores 1 as it is switched • off permanently • NOR Flash memories have • Fast random read time • Slow erasure and programming time • Need precise control of thresholds

34. Word line(poly) Unit Cell Source line (Diff. Layer) NAND Flash Memory High dielectric material – oxide-nitride-oxide for large CFG Select transistors Large storage density lower cost Fast programming 200-400 nsec Fast serial access Courtesy Toshiba

35. Select transistor Word lines Active area STI Bit line contact Source line contact NAND Flash Memory All contacts between word line are eliminated resulting in 40% smaller cell than NOR structure During erasure all transistor are depletion mode obtained by setting 20V at the source During program the selected word line is set to 20V to store “1” increasing its threshold During read both select transistors are enabled and read proceeds as in the NAND ROM Courtesy Toshiba

36. New Nonvolatile Memories • FRAM – Ferroelectric RAM • Uses programmable capacitors • Dielectric cristals polarize under electric field • Very high density, many read/write cycles, • Low power • MRAM – Magnetoresistive RAM • Similar to magnetic core memories • Spin electronic or tunneling magnetic resistance

37. Characteristics of State-of-the-art NVM

38. Read-Write Memories (RAM) • STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential • DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

39. Q 6-transistor CMOS SRAM Cell WL V DD M M 2 4 Q M M 6 5 M M 1 3 BL BL

40. CMOS SRAM Analysis (Read) WL V DD M BL 4 BL Q 0 = M Q 1 = 6 M 5 V V V M DD DD DD 1 C C bit bit Initially BL and BLbar are precharged. Assume that cell stores 1 When the WL goes high BLbar is discharged low Must keep Qbar voltage rise below the nMOS threshold (0.4V) to avoid flipping the cell

41. CMOS SRAM Analysis (Read) 1.2 Cell ratio 1 0.8 0.6 0.4 Design for cell ratio in the green zone 0.2 0 0 0.5 1.2 1 1.5 2 2.5 3 Voltage Rise (V) Cell Ratio (CR)

42. WL V DD M 4 M Q 0 = 6 M 5 Q 1 = M 1 V DD BL 1 BL 0 = = CMOS SRAM Analysis (Write)

43. CMOS SRAM Analysis (Write) Must pull down cell voltage VQbelow the nMOS threshold (0.4V)

44. VDD M2 M4 Q Q M1 M3 GND M5 M6 WL BL BL 6T-SRAM — Layout

45. WL V DD R R L L Q Q M M 3 4 BL BL M M 1 2 Static power dissipation -- Want R large L Bit lines precharged to V to address t problem DD p Resistance-load SRAM Cell For large resistor values use undoped polysilicon with sheet resistance in Tohm/sq An alternative solution uses low quality parasitic thin-film PMOS (TFT) with OFF current 10-13A

46. WL V DD R R L L Q Q M M 3 4 BL BL M M 1 2 Static power dissipation -- Want R large L Bit lines precharged to V to address t problem DD p Resistance-load SRAM Cell For large resistor values use undoped polysilicon with sheet resistance in Tohm/sq An alternative solution uses low quality parasitic thin-film PMOS (TFT) with OFF current 10-13A

47. Bit Bit Bit Bit Bit Bit Word M8 M9 M4 M5 CAM ••• CAM M6 M7 Word S S Word int CAM ••• CAM M3 M2 Match M1 Wired-NOR Match Line Static CAM Memory Cell Incoming data on Bit and Bit_bar are compared with the stored data S and S_bar Match line is precharged high ••• ••• If there is a match the internal signal int is grounded and match stays high Otherwise int is pulled high and match goes low

48. SRAM Characteristics

49. BL 1 BL 2 WWL WWL RWL RWL M 3 V V X M X 2 DD T 1 M 2 V DD BL 1 C S V D BL 2 V V 2 DD T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V -V WWL Tn 3-Transistor DRAM Cell

50. BL2 BL1 GND RWL M3 M2 WWL M1 3T-DRAM — Layout