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Lecture 5

Lecture 5. Interrupts & Interconnects. Functional Description. The interrupt controller processes incoming interrupts By masking and priority sorting to produce the interrupt signals for the processor to which it is attached Input Selection

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Lecture 5

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  1. Lecture 5 Interrupts & Interconnects NCHUEE 720A Lab Prof. Jichiang Tsai

  2. Functional Description • The interrupt controller processes incoming interrupts • By masking and priority sorting to produce the interrupt signals for the processor to which it is attached • Input Selection • The INTC supports only level-sensitive incoming interrupt detection. • A peripheral asserting an interrupt maintains it until software has handled the interrupt and instructed the peripheral to deassert the interrupt • A software interrupt is generated if the corresponding bit in the MPU_INTC.INTC_ISR_SETn register is set • Register bank number: n = [0,1,2,3] for the MPU subsystem INTC, 128 incoming interrupt lines are supported • The software interrupt clears when the corresponding bit in the MPU_INTC.INTC_ISR_CLEARn register is written • Typical use of this feature is software debugging NCHUEE 720A Lab Prof. Jichiang Tsai

  3. Interrupt Controller Block Diagram NCHUEE 720A Lab Prof. Jichiang Tsai

  4. Functional Description (cont.) • Individual Masking • Detection of interrupts can be enabled or disabled independently • By the MPU_INTC.INTC_MIRn interrupt mask register • In response to an unmasked incoming interrupt, the INTC can generate one of two types of interrupt requests to the processor • IRQ: low-priority interrupt request • FIQ: fast interrupt request • The type of interrupt request is determined by the MPU_INTC.INTC_ILRm[0] FIQNIRQ bit (m= [0,127]) • The current incoming interrupt status before masking is readable from the MPU_INTC.INTC_ITRn register • After masking and IRQ/FIQ selection, and before priority sorting is done, the interrupt status is readable from • The MPU_INTC.INTC_PENDING_IRQn and MPU_INTC.INTC_PENDING_FIQn registers NCHUEE 720A Lab Prof. Jichiang Tsai

  5. Functional Description (cont.) • Priority Masking • To enable faster processing of high-priority interrupts, a programmable priority masking threshold is provided • The MPU_INTC.INTC_THRESHOLD[7:0] PRIORITYTHRESHOLD field • This threshold allows preemption by higher priority interrupts • All interrupts of lower or equal priority than the threshold are masked • Priority 0 can never be masked by this threshold • A priority threshold of 0 is treated the same way as priority 1 • Priority threshold values can be set between 0x0 and 0x7F • 0x0 is the highest priority and 0x7F is the lowest priority • When priority masking is not necessary, a priority threshold value of 0xFF disables the priority threshold mechanism • This value is also the reset default for backward compatibility with previous versions of the INTC NCHUEE 720A Lab Prof. Jichiang Tsai

  6. Functional Description (cont.) • Priority Sorting • A priority level is assigned to each incoming interrupt line • 0 is the highest • Both the priority level and the interrupt request type are configured by the MPU_INTC.INTC_ILRm register • If more than one incoming interrupt with the same priority level and interrupt request type occur simultaneously • The highest-numbered interrupt is serviced first • When one or more unmasked incoming interrupts are detected • The INTC separates between IRQ and FIQ using the corresponding MPU_INTC.INTC_ILRm[0] FIQNIRQ bit • The result is placed in INTC_PENDING_IRQn or INTC_PENDING_FIQn • If no other interrupts are currently being processed, INTC asserts IRQ/FIQ and starts the priority computation NCHUEE 720A Lab Prof. Jichiang Tsai

  7. Functional Description (cont.) • Priority sorting for IRQ and FIQ can execute in parallel • Each priority sorter determines the highest priority interrupt number • Each priority number is placed in the corresponding MPU_INTC.INTC_SIR_IRQ[6:0] ACTIVEIRQ field or MPU_INTC.INTC_SIR_FIQ[6:0] ACTIVEFIQ field • The value is preserved until the corresponding MPU_INTC.INTC_CONTROL NEWIRQAGR or NEWFIQAGR bit is set • Once the interrupting peripheral device has been serviced and the incoming interrupt deasserted • The user must write to the appropriate NEWIRQAGR or NEWFIQAGR bit to indicate to the INTC the interrupt has been handled • If there are any pending unmasked incoming interrupts for this interrupt request type • The INTC restarts the appropriate priority sorter • Otherwise, the IRQ or FIQ interrupt line is deasserted NCHUEE 720A Lab Prof. Jichiang Tsai

  8. Module Power Saving • The INTC provides an auto-idle function in its three clock domains • Interface clock • The interface clock auto-idle power-saving mode is enabled • If the MPU_INTC.INTC_SYSCONFIG[0] AUTOIDLE bit is set to 1 • When there is no activity on the bus interface, the interface clock is disabled internally to the module • When there is new activity on the bus interface, the interface clock restarts without any latency penalty • After reset, this mode is disabled, by default • Functional clock • The functional clock auto-idle power-saving mode is enabled • If the MPU_INTC.INTC_IDLE[0] FUNCIDLE bit is set to 0 NCHUEE 720A Lab Prof. Jichiang Tsai

  9. Module Power Saving (cont.) • When there is no active interrupt or no pending incoming interrupt, the functional clock is disabled internally to the module • When a new unmasked incoming interrupt is detected, the functional clock restarts and the INTC processes the interrupt • If this mode is disabled, the interrupt latency is reduced by one cycle • After reset, this mode is enabled, by default • Synchronizer clock • The synchronizer clock allows external asynchronous interrupts to be resynchronized before they are masked • The synchronizer clock has an auto-idle power-saving mode enabled • If the MPU_INTC.INTC_IDLE[1] TURBO bit is set to 1 • If the auto-idle mode is enabled, the standby power is reduced, • The interrupt latency increases from four to six functional clock cycles • Can be enabled dynamically according to the requirements of the device • After reset this mode is disabled, by default NCHUEE 720A Lab Prof. Jichiang Tsai

  10. Error Handling • The following accesses will cause an error • Privilege violation • Attempt to access PROTECTION register in user mode or any register in user mode if Protection bit is set • If the MPU_INTC.INTC_PROTECTION[0] PROTECTION bit is set, access to the INTC registers is restricted to the supervisor mode • Access to the MPU_INTC.INTC_PROTECTION register is always restricted to privileged mode • Unsupported commands • The following accesses will not cause any error response • Access to a non-decoded address • Write to a read-only register NCHUEE 720A Lab Prof. Jichiang Tsai

  11. Interrupt Handling • The IRQ/FIQ interrupt generation takes four INTC functional clock cycles (plus or minus one cycle) • If the MPU_INTC.INTC_IDLE[1] TURBO bit is set to 0 • If the TURBO bit is set to 1, the generation takes six cycles • Power consumption is reduced while waiting for an interrupt • These latencies can be reduced by one cycle • By disabling functional clock auto-idle • MPU_INTC.INTC_IDLE[0] FUNCIDLE bit setto 1 • Power consumption is increased, so the benefit is minimal • To minimize interrupt latency for an unmasked interrupt • The interrupt is generated before priority sorting completion • The priority sorting takes 10 functional clock cycles NCHUEE 720A Lab Prof. Jichiang Tsai

  12. Interrupt Handling (cont.) • Less than the minimum number of cycles required for the MPU to switch to the interrupt context after reception of the IRQ or FIQ event • Before priority sorting is complete and the relevant register is updated • Any read of the MPU_INTC.INTC_SIR_IRQ or MPU_INTC.INTC_SIR_FIQ register during the priority sorting process stalls • Priority sorting always completes before the MPU_INTC.INTC_SIR_IRQ or MPU_INTC.INTC_SIR_FIQ register is read NCHUEE 720A Lab Prof. Jichiang Tsai

  13. Initialization Sequence • Program the MPU_INTC.INTC_SYSCONFIG register • If necessary, enable the interface clock autogating • By setting the AUTOIDLE bit • Program the MPU_INTC.INTC_IDLE register • If necessary, disable functional clock autogating or enable synchronizer autogating • By setting the FUNCIDLE bit or TURBO bit • Program the MPU_INTC.INTC_ILRm register for each interrupt line • Assign a priority level • Set the FIQNIRQ bit for an FIQ interrupt • By default, interrupts are mapped to IRQ and priority is 0x0 [highest] NCHUEE 720A Lab Prof. Jichiang Tsai

  14. Initialization Sequence (cont.) • Program the MPU_INTC.INTC_MIRn register • Enable interrupts • By default, all interrupt lines are masked). • To program the MPU_INTC.INTC_MIRn register • The MPU_INTC.INTC_MIR_SETn and MPU_INTC.INTC_MIR_CLEARn registers are provided to facilitate the masking, • It is possible for backward-compatibility to write directly to the MPU_INTC.INTC_MIRn register NCHUEE 720A Lab Prof. Jichiang Tsai

  15. INTC Processing Sequence • IRQ and FIQ processing sequences are quite similar • One or more unmasked incoming interrupts (M_IRQ_n signals) are received and IRQ or FIQ outputs (IRQ/FIQ) are not currently asserted • If the INTC_ILRm[0] FIQNIRQ bit is cleared to 0, the MPU_INTC_IRQ output signal is generated • If FIQNIRQ is set to 1, the MPU_INTC_FIQ signal is generated • The INTC performs the priority sorting and updates the INTC_SIR_IRQ[6:0] ACTIVEIRQ/INTC_SIR_FIQ[6:0] ACTIVEFIQ field with the current interrupt number • During priority sorting, if the IRQ/FIQ is enabled at the host processor side, the host processor automatically saves the current context and executes the ISR NCHUEE 720A Lab Prof. Jichiang Tsai

  16. INTC Processing Sequence (cont.) • The ISR saves the remaining context, identifies the interrupt source by reading the ACTIVEIRQ/ACTIVEFIQ field • Jumps to the relevant subroutine handler • The subroutine handler executes code specific to the peripheral generating the interrupt • By handling the event and deasserting the interrupt condition at the peripheral side • After the return of the subroutine, the ISR sets the NEWIRQAGR/NEWFIQAGR bit • To enable the processing of subsequent pending IRQs/FIQs and to restore ARM context • The INTC processes any other pending interrupts or deasserts the IRQ/FIQ signal if there is no interrupt • Priority sorting is reactivated NCHUEE 720A Lab Prof. Jichiang Tsai

  17. INTC Interrupt Preemption • Preemptive interrupts can reduce the latencies for higher priority interrupts • Also called nested interrupts • A preemptive ISR can be suspended by a higher priority interrupt • The higher priority interrupt can be served immediately • Nested interrupts must be used carefully to avoid using corrupted data • Programmers must save corruptible registers and enable IRQ or FIQ at ARM side • To enable IRQ/FIQ preemption • At the beginning of an IRQ/FIQ ISR • Save the ARM critical context registers NCHUEE 720A Lab Prof. Jichiang Tsai

  18. INTC Interrupt Preemption (cont.) • Save the INTC_THRESHOLD PRIORITYTHRESHOLD field before modifying it • Read the active interrupt priority in the INTC_IRQ_PRIORITY IRQPRIORITY/INTC_FIQ_PRIORITY FIQPRIORITY field • Write it to the PRIORITYTHRESHOLD field • Read the active interrupt number in the INTC_SIR_IRQ[6:0] ACTIVEIRQ/INTC_SIR_FIQ[6:0] ACTIVEFIQ field • To identify the interrupt source • Write 1 to the appropriate INTC_CONTROL NEWIRQAGR and NEWFIQAGR bit while an interrupt is still processing • To allow only higher priority interrupts to preempt • Because the writes are posted on an Interconnect bus, to be sure that the preceding writes are done before enabling IRQs/FIQs • Enable IRQ/FIQ at ARM side • Jump to the relevant subroutine handler NCHUEE 720A Lab Prof. Jichiang Tsai

  19. INTC Interrupt Preemption (cont.) • After the return of the relevant IRQ/FIQ subroutine handle • Disable IRQs/FIQs at ARM side • Restore the INTC_THRESHOLD PRIORITYTHRESHOLD field • Restore the ARM critical context registers • For each level of preemption, we must save the threshold value before modifying it and restore it at the end of that ISR level • The priority threshold mechanism is enabled automatically when writing a priority in the range of 0 to 7Fh • As will be read from IRQ_PRIORITY and FIQ_PRIORITY • Writing a value of FFh (reset default) disables the mechanism • When the hardware priority threshold is in use • The priorities of interrupts selected as FIQ or IRQ become linked • Otherwise, they are independent NCHUEE 720A Lab Prof. Jichiang Tsai

  20. INTC Interrupt Preemption (cont.) • When linked, it is required that all FIQ priorities be set higher than all IRQ priorities to maintain the relative priority of FIQ over IRQ • When handling FIQs using the priority threshold mechanism • It is required to cover the case that the new priority threshold is applied while an IRQ sorting is in progress • Writing New FIQ Agreement and New IRQ Agreement bits simultaneously • IRQ will not have been seen by the ARM as it will have been masked on entry to the FIQ ISR • The source of the IRQ will remain active and it will be finally processed when the priority threshold falls to a low enough priority • The precaution of writing to New FIQ Agreement (as well as New IRQ Agreement) is not required during an IRQ ISR • FIQ sorting will not be affected • Provided all FIQ priorities are higher than all IRQ priorities NCHUEE 720A Lab Prof. Jichiang Tsai

  21. INTC Spurious Interrupt Handling • The spurious flag indicates whether the result of the sorting is invalid • A window of 10 INTC functional clock cycles after the interrupt assertion • The sorting is invalid if: • The interrupt is no longer active during the sorting • A change in the mask has affected the result during the sorting time • The values in the INTC_MIRn, INTC_ILRm, or INTC_MIR_SETn registers must not be changed • While the corresponding interrupt is asserted • Only the active interrupt input that triggered the sort can be masked before it turn on the sort • If these registers are changed within the 10-cycle window NCHUEE 720A Lab Prof. Jichiang Tsai

  22. INTC Spurious Interrupt Handling (cont.) • The values of the INTC_SIR_IRQ, INTC_SIR_FIQ, INTC_IRQ_ PRIORITY and INTC_FIQ_PRIORITY registers become invalid • This condition is detected for both IRQ and FIQ • The invalid status is flagged across the SPURIOUSIRQFLAG and SPURIOUSFIQFLAG bit fields in the SIR and PRIORITY registers • A 0 indicates valid and a 1 indicates invalid interrupt number and priority • The invalid indication can be tested in software as a false register value • ARM Cortex-A8 Interrupts NCHUEE 720A Lab Prof. Jichiang Tsai

  23. Interconnects • The decoding, routing, and arbitration logic • Enables the connection between multiple initiator modules and multiple target modules connected on it • Initiator: Module able to initiate read and write requests to the chip interconnect (typically: processors, DMA, etc.) • Target: A target module cannot generate read/write requests to the chip interconnect, but it can respond to these requests • It may generate interrupts or a DMA request to the system • Typically: peripherals, memory controllers • A module can have several separate ports • A module can be an initiator and a target • The system interconnect is based on a 2-level hierarchical architecture (L3, L4) driven by system performance • The L4 interconnect is based on a fully native OCP infrastructure NCHUEE 720A Lab Prof. Jichiang Tsai

  24. Interconnects (cont.) • Each connection of one module to one interconnect is done using an agent • An adaptation between the module and the interconnect • Sometimes configurable • A target module is connected by a target agent (TA) • An initiator module is connected by an initiator agent (IA) • Register Target (RT): Special TA used to access the interconnect internal configuration registers • Data-flow Signal: Any signal that is part of a clearly identified transfer or data flow • Typically: command, address, byte enables, etc. • Signal behavior is defined by the protocol semantics • Sideband Signal: Any signal whose behavior is not associated to a precise transaction or data flow NCHUEE 720A Lab Prof. Jichiang Tsai

  25. Interconnects (cont.) • A command slot is a subset of the command list • It is the memory buffer for a single command • A total of 32 command slots exist • Out-of-band Error: Any signal whose behavior is associated to a device error-reporting scheme • Interrupt requests and DMA requests are not routed by the interconnect in the device • ConnID: Any transaction in the system interconnect is tagged by an in-band qualifier ConnID • Uniquely identifies the initiator at a given interconnect point • A ConnID is transmitted in band with the request and is used for error-logging mechanism NCHUEE 720A Lab Prof. Jichiang Tsai

  26. L3 Interconnect • The L3 high-performance interconnect is based on a Network-On-Chip (NoC) interconnect infrastructure • The NoC uses an internal packet-based protocol for forward and backward transactions • Forward: Read command, write command with data payload • Backward: Read response with data payload, write response • All exposed interfaces of this NoC interconnect, both for Targets and Initiators, comply with OCPIP2.2 • The L3 topology is driven by performance requirements, bus types, and clocking structure • L3 is partitioned into two separate clock domains • L3F corresponds to L3 Fast clock domain • L3S corresponds to L3 Slow clock domain NCHUEE 720A Lab Prof. Jichiang Tsai

  27. L3 Topology • Arrows indicate the master/slave relationship NCHUEE 720A Lab Prof. Jichiang Tsai

  28. L3 Interconnect (cont.) • Each initiator and target core is connected to the L3 interconnect through a Network Interface Unit (NIU) • Acts as an entry and an exit points to the L3 Network on Chip • Converting between the IP’s OCP protocol and the NoC’s internal protocol, and also include various programming registers • All ports are single threaded with tags used to enable pipelined transactions • Initiator Ports • L3F • Cortex A8 MPUSS 128-bit initiator port0 and 64-bit initiator port1 • SGX530 128-bit initiator port and LCDC 32-bit initiator port • 3 TPTC 128-bit read initiator ports and 128-bit write initiator ports • 2 PRU-ICSS1 32-bit initiator ports & debug subsystem 32-bit initiator port • 2 port Gigabit Ethernet Switch (2PGSW) 32-bit initiator port NCHUEE 720A Lab Prof. Jichiang Tsai

  29. L3 Interconnect (cont.) • L3S • USB 32-bit CPPI DMA initiator port & 32-bit queue manager initiator port • P1500 32-bit initiator port • Target Ports • L3F • EMIF 128-bit target port and OCM RAM0 64-bit target port • 3 TPTC CFG 32-bit target ports and TPCC CFG 32-bit target port • DebugSS32-bit target port and SGX530 64-bit target port • L4_FAST 32-bit target port • L3S • 4 L4_PER peripheral 32-bit target ports and GPMC 32-bit target port • McASP0 32-bit target port and McASP1 32-bit target port • ADC_TSC 32-bit target port and USB 32-bit target port • MMHCS2 32-bit target port and L4_WKUP wakeup 32-bit target port NCHUEE 720A Lab Prof. Jichiang Tsai

  30. L3 Interconnect (cont.) • The required L3 connections between bus masters and slave ports • The L3 interconnect will return an address-hole error • If any initiator attempts to access a target to which it has no connection • Each L3 initiator includes a unique 6-bit master connection identifier (MConnID) • Used to indentify the source of a transfer request • Since AM335x contains more than 16 unique masters, some masters will appear identical to target firewalls NCHUEE 720A Lab Prof. Jichiang Tsai

  31. Interconnect Requirements NCHUEE 720A Lab Prof. Jichiang Tsai

  32. MConnID Assignment NCHUEE 720A Lab Prof. Jichiang Tsai

  33. L4 Interconnect • A non-blocking peripheral interconnect • Provides low latency access to a large number of low bandwidth, physically dispersed target cores • The L4 can handle incoming traffic from up to four initiators • Can distribute those communication requests to and collect related responses from up to 63 targets • AM335x provides three interfaces with L3 interconnect • For High Speed Peripheral, Standard Peripheral, and Wakeup Peripherals NCHUEE 720A Lab Prof. Jichiang Tsai

  34. L4 Topology NCHUEE 720A Lab Prof. Jichiang Tsai

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