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MIMOSA22  MIMOSA26  ULTIMATE

MIMOSA22  MIMOSA26  ULTIMATE. Christine HU-GUO (IPHC-Strasbourg). MIMOSA22. AMS-OPTO 0.35 µm Dim. pixel 18.4 x 18.4 µm² Dim. Matrice 136 x 576 pixels 8 sorties analogiques 128 sorties numériques Vitesse d’intégration < 100µs Slow Control : JTAG Références internes (DAC)

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MIMOSA22  MIMOSA26  ULTIMATE

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  1. MIMOSA22  MIMOSA26  ULTIMATE Christine HU-GUO (IPHC-Strasbourg)

  2. MIMOSA22 • AMS-OPTO 0.35µm • Dim. pixel 18.4 x 18.4 µm² • Dim. Matrice 136 x 576 pixels • 8 sorties analogiques • 128 sorties numériques • Vitesse d’intégration < 100µs • Slow Control : JTAG • Références internes (DAC) • Lecture multiplexée  50 MHz • Non inclus: suppression de zéros • Soumission : octobre 2007 • Retour de fonderie : janvier 2008 STAR meeting IPHC christine.hu@ires.in2p3.fr

  3. Slct_Row Slct_Row Slct_Gr 16 pix Slct_Row Slct_Row Slct_Row Slct_Gr 16 pix Slct_Row Slct_Row Slct_Row Slct_Gr 16 pix Slct_Row Column –level discriminator RD CALIB LATCH In Pixel amplification & Signal Processing (1) Integrated in Discri. • 4 digital control signals per row: PWR_On, Slct_Row, Slct_Grp, Clamping • Slct_Row (16xCK), PWR_On (2x16xCK), Slct_Gr (16x16xCK): power activate signals • Clp: signal for CDS (3xCK) STAR meeting IPHC christine.hu@ires.in2p3.fr

  4. M4 M5 Low-pass filter M3 feedback Pdiff / Nwell M2 Nwell / Pepi signal current In Pixel amplification & Signal Processing (2) • Common Source (CS) amplification in pixel • Only NMOS transistors can be used 1 2 3 CS + Reset Improved CS + Reset Improved CS + Feedback + Self biased M4 bias bias reset reset M3 M3 out out M1 M1 Nwell / Pepi M2 M2 Nwell / Pepi signal current signal current a negative low frequency feedback was introduced to decrease amplification gain variations due to process variations STAR meeting IPHC christine.hu@ires.in2p3.fr

  5. 3 3 1 1 2 2 2 2 1 1 3 3 In Pixel amplification & Signal Processing (3) • Measured Mimosa22 pixel (Amp+CDS) performances (20 °C) before irradiation: • After ionizing irradiation, feedback self-biased structure has the best performances (conditions: +20C, integration time ~92μs) 1 2 3 3 BUT from previous studies (MIMOS15) on chips without in-pixel signal processing the noise was in order of ~15e after dose of 1MRad STAR meeting IPHC christine.hu@ires.in2p3.fr

  6. M4 M5 Low-pass filter M3 feedback Pdiff / Nwell M2 Nwell / Pepi signal current Increasing Radiation Tolerance in Pixel • Ionizing radiation tolerance (22bis, 22ter): • Pixel circuit level: • ELT for the transistor connected to the detection diode • Diode level: • Remove thick oxide surrounding N-well diode by replacing with thin-oxide • Non-ionizing radiation tolerance: • Reducing pixel pitch  pitch < 20 µm  18.4 µm • Increasing sensing diode size: limited by layout • Reducing integration time  ~100-200 µs STAR meeting IPHC christine.hu@ires.in2p3.fr

  7. Vclp_d RD REF1 RD RD REF2 Q CALIB LATCH To Pixel RD RD LATCH Vclp_d RD CALIB Q Column-level discriminators • Discriminator design considerations: • Small input signal  Offset compensated amplifier stage • Dim: 16.4 x 430 µm2 • Conversion time = row read out time (~200 ns) • Consumption ~230 µW Column-level Double Sampling (DS) reduce pixel to pixel dispersion (FPN) STAR meeting IPHC christine.hu@ires.in2p3.fr

  8. 0.3 mV 0.2 mV Column-level discriminators: characterizations Analyze Method • Scan threshold voltage (N discri.) • Fit to an error function • Mean Offset • Sigma temporal noise (TN) • Mean of N sigma  average of TN • RMS of N offsets  FPN Resultants • FPN : 0.2 mV • TN : 0.3 mV STAR meeting IPHC christine.hu@ires.in2p3.fr

  9. Test in lab: Temporal Noise: 0.64 mV  11.5 e- FPN: 0.22 mV  3.9 e- Beam test with 120 GeV pions at CERN-SPS Threshold ~ 4 mV  6 σ noise 0.64 mV 0.22 mV Mimosa22 test results: Pixels + 128 Discriminators • Detection efficiency > 99.5% • Spatial resolution < 4 µm • Fake rate < 10-4 STAR meeting IPHC christine.hu@ires.in2p3.fr

  10. MIMOSA26: 1st Sensor with Integrated Ø Chip size : 13.8 x 21.6 mm2, AMS C35B4: 0.35µm technology • Pixel array: 576 x 1152, pitch: 18.4 µm • Active area: ~10.6 x 21.2 mm2 • In each pixel: • Amplification • CDS (Correlated Double Sampling) • Testability: several test points implemented all along readout path • Pixels out (analogue) • Discriminators • Zero suppression • transmission Row sequencer Width: ~350 µm • 1152 column-level discriminators • offset compensated high gain preamplifier followedby latch Zero suppression logic Reference Voltages Buffering for 1152 discriminators I/O PadsPower supply PadsCircuit control PadsLVDS Tx & Rx Current Ref. Bias DACs Readout controller JTAG controller Memory management Memory IP blocks Test blocksPLL, 8b/10b STAR meeting IPHC christine.hu@ires.in2p3.fr

  11. Vclp_d RD REF1 RD RD REF2 Q CALIB LATCH To Pixel RD RD LATCH Vclp_d RD CALIB DAC DAC REF Q 288 discriminators 288 discriminators 288 discriminators 288 discriminators DAC discriminator discriminator discriminator DAC 1152 discriminators Readout Chain: Pixel + discriminator • Reference voltages (threshold) & clamping voltage are analogue signals which have to apply to 1152 discriminators • Need stable signals during "RD" & "CALIB" periods • Ex. RD (3 CK  ~ 30 ns) • Need to drive ~2 cm long line • RC distribution line + successive charge rejections • Even an ideal voltage source CANNOT satisfy these requirements • 1152 discriminators are divided into 4 groups, 4 bias DAC • compensate process dispersions of discriminators STAR meeting IPHC christine.hu@ires.in2p3.fr

  12. Readout Chain: zero suppression + memories ………… • Connected to column-level discriminators outputs • Zero suppression is based on row by row sparse data scan readout and organized in pipeline mode in three steps: Pixel Array Column 0 Column 1152 ………… Discriminators A/D A/D Core of the zero suppression ………… Sparse Data Scan (N states) Sparse Data Scan (N states) Sparse Data Scan (N states) Retaining M states per row (+ addresses) among 18 banks Memory 0 Memory 1 Serial transmission STAR meeting IPHC christine.hu@ires.in2p3.fr

  13. Readout Chain: zero suppression + memories • 1st step: • 1152 columns terminations 18 banks // scan • Based on a sparse data scan algorithm to find hit pixels (discriminator output = "1") • Up to 4 contiguous pixel signals above Vth will be encoded in a 2 bits state word following by address of the 1st pixel • Find up to N states with column addresses per bank ………… Column 0 Column 1152 ………… A/D A/D Core of the zero suppression ………… Sparse Data Scan (N states) Sparse Data Scan (N states) Sparse Data Scan (N states) Retaining M states per row (+ addresses) among 18 banks Memory 0 Memory 1 Serial transmission STAR meeting IPHC christine.hu@ires.in2p3.fr

  14. Readout Chain: zero suppression + memories …….… Row M-1 state Row M state Row M+1 state ……..….… HIT State Binary code 00 1 0 0 0 Row M 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 01 1 1 0 0 10 1 1 1 0 State 1 State 2 11 1 1 1 1 2 bits binary code Column address of the 1st pixel State: Column address of the 1st pixel+ 2 bits code STAR meeting IPHC christine.hu@ires.in2p3.fr

  15. Readout Chain: zero suppression + memories ………… • 2nd step: • Read out the outcomes of the 1st step in all banks and keep up to M states • Add row and bank addresses Column 0 Column 1152 ………… A/D A/D Core of the zero suppression ………… Sparse Data Scan (N states) Sparse Data Scan (N states) Sparse Data Scan (N states) Retaining M states per row (+ addresses) among 18 banks Memory 0 Memory 1 Serial transmission STAR meeting IPHC christine.hu@ires.in2p3.fr

  16. Readout Chain: zero suppression + memories ………… N, M, Memory capacity and Memory Read-out speed depend on hit density  N = 6, M = 9, Memory ~ 40 Kbits, Nominal Read-out Freq.: 80 MHz • 3rd step: • Store the outcomes of the 2nd step to a memory • The memory is made of 2 IP's buffers  continuous read-out • 1 buffer stores current frame, 1 buffer is read out previous frame • Serial transmission by LVDS pad ………… S0 ………… S1 ………… S17 Column 0 Column 1152 Column 0 Column 63 Column 0 Column 63 Column 0 Column 63 ………… A/D A/D Core of the zero suppression ………… Sparse Data Scan (N states) Sparse Data Scan (N states) Sparse Data Scan (N states) Retaining M states per row (+ addresses) among 18 banks Memory 0 Memory 1 Serial transmission STAR meeting IPHC christine.hu@ires.in2p3.fr

  17. Test MIMOSA26 • Mimosa26 returned from foundry on February 2009. • Extensive tests are going on in the laboratory. • Measured temporal noise = 0.6-0.7 mV and FPN = 0.3-0.4 mV for pixel array with its associated discriminators. • These values are equivalent to those obtained with Mimosa22. • Figures show measured results for one quarter of the matrix with column-level discriminators. The remaining three quarters of the matrix exhibit similar performances showing a good uniformity of the whole 576 x 1152 pixels with the 1152 discriminators • The characterization of Mimosa26 will be completed by the beam tests planned in Summer 2009 + yield evaluation STAR meeting IPHC christine.hu@ires.in2p3.fr

  18. MIMOSA26  ULTIMATE • Zero suppression: physics condition : 2,4 x 105 hits/s/cm2 • Readout time 200 µs  ~ 200 hits/frame/sensor • The highest luminosity expected at STAR for RHIC2 gives: • 60 hits / cm2 , s = 8 hits • On the inner layer of sensors in a 200 µs integration window. • This rate is for interactions and peripheral collisions. Possible background sources are not included. • ~450 hits /sensor • 450 hits + 240 Noisy pixels • > 5s & ~2x10-4 noisy pixels • Safety factor ? • SUZE design: • Maximum output speed: ~100 Mbits/s • 2 memories of (200 x 3) x 32 bits • With new condition & with ~ 10-4  ~ 100 noisy pixels • Zero suppression  based on SUZE's group & row hits finders design • Points have to be changed: • Increase maximum output speed: up to 256 Mbits/s • Increase dimension of memory: > 3 times larger (2048 x 32)x2 • Memory: anti latch up?  530 hits /frame equivalent STAR meeting IPHC christine.hu@ires.in2p3.fr

  19. Power Consumption 500 hits STAR meeting IPHC christine.hu@ires.in2p3.fr

  20. Frequency distribution • Circuit needs: • CK : 80 MHz • Pixels & Comparators: 16 CK  5 MHz • SUZE CK: 80 MHz • LVDS out: 2 x 120 MHz  2 x 160 MHz • Input Freq.: • 160 MHz external CK • Option: 80 MHz external CK • Option: 10 MHz external CK, PLL (N=16) output Freq.: 160 MHz • 80 MHz will be made in chip • Possibility to integrate 8b/10b encoding to allow reasonable clock recovery • Option for the Ultimate1 chip Pixels & Comparators 8b/10b 16 MHz 80 MHz ÷ 10 ÷ 2 160MHz LVDS PLL (N=16) LVDS LVDS 10MHz 160MHz STAR meeting IPHC christine.hu@ires.in2p3.fr

  21. Ultimate Sensor Testing Functionality (implemented in MIMOSA26) Analogue pixels outputs Pixel Array switch Inject 2 Test Voltages to emulate pixels outputs comparators Read One Row Register, Pixels & Comparators are in normal mode, tint = 200µs, Readout freq. = 5 MHz via 2 LVDS output pads. The auto increment functional logic to scan whole matrix will be studied. switch switch Inject 2 SUZE Test Rows SUZE 160 MHz switch Inject Test Pattern of 32 bits to emulate memory outputs 5 MHz 5 MHz 5 MHz 160 MHz MUX MUX MUX Data CK LVDS LVDS LVDS STAR meeting IPHC christine.hu@ires.in2p3.fr

  22. Latch-up STAR meeting IPHC christine.hu@ires.in2p3.fr

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