A Power-Constrained MPU Roadmap for I nternational T echnology R oadmap for S emiconductors

1. A Power-Constrained MPU Roadmap for International Technology Roadmap for Semiconductors Kwangok Jeong and Andrew B. Kahng UCSD VLSI CAD Laboratory abk@cs.ucsd.edu CSE and ECE Department University of California, San Diego

2. Needs for MPU Roadmap • What is the limit of future SoC designs? • MPU uses highest frequency / power / integration level of a technology  MPU is a reference of leading edge SoC designs • For a good MPU roadmap, • How would you approach the task of roadmapping MPU? • On what technology parameters should the MPU roadmap depend? • What constraints cause fundamental shifts in the MPU roadmap? • A consistent and holistic modeling approach for MPU roadmap to reflect recent technology changes and to tradeoff MPU design constraints • Historical MPU design constraints • Moore’s Law: #TrN = 2  (#TrN-1) • Constant die area: 310mm2 ((2X #Tr)  (0.5X Tr area) = 1) • Power: 130W ~ 150W • Performance: improved with multicore architecture

3. Technology Scaling Changes for ITRS 2009 • New scaling trends for M1 half pitch and gate length • Cell area follows M1 half pitch • Electrical parameter follows gate length • Smaller area is expected, but what about power? 2 year delayed, but scaling becomes more aggressive 0.7x / 3year  0.7x / 2year (~2013), 0.7x / 3year (2014~) M1 ½ Pitch • Decreases dimension • Smaller area • Decreases Pdyn and Pleak • Increases density • Increases Pdyn and Pleak Physical Lgate 1 year delayed • Electrical Parameters (Ioff, Cunit, etc.) • Increases gate capacitance • Decreases Ioff • Increases Pdyn but decreases Pleak

4. Parameterized MPU Model Metal1 (M1) Pitch M1 Half-Pitch (F) Unit Cell Layout Unit logic cell width (Wlogic) Unit logic cell height (Hlogic) Unit SRAM bitcell width (WSRAM) Unit SRAM bitcell height (HSRAM) A-Factor (Alogic ,ASRAM) M1 half-pitch (F) = M1 pitch / 2 Unit-Cell Area (Ulogic ,USRAM) Design Rules #Components Metal2 routing pitch (pM2) Poly-to-poly pitch (ppoly) #Tr. per logic cell (Ntr,nand2) #Tr. per SRAM bitcell (Ntr,bitcell) #Logic gates per core (Ngates) #Bitcells per core (Nbits) #Cores per die (Ncore) Transistor Density (Dlogic ,DSRAM) Design Overhead Logic layout overhead (Ologic) SRAM layout overhead (OSRAM) Technology (PIDS) Capacitance Density (Dcap,logic , Dcap,SRAM , Dcap,int) Gate length (Lg) Gate width (Wg) Gate capacitance (Cg) Technology (Interconnect) Interconnect capacitance (Cint) Interconnect density (Dl,max) Power Density (Ddynamic ,Dstatic) Unit-width leakage (Ioff) Operating Condition Low Power Tech. Voltage (V) Frequency (f) MPU Power (P) Switching ratio () Low-Vth cell ratio ()

5. Updated A-Factors: M1 HP (F) based Model • SRAM: • A-factor = 60 SRAM Bitcell Area = 2 PPoly 5 PM1 = 3 PM1  5 PM1= 15 (PM1)2 = 15 (2 F)2 = 60 F2 • Logic: • A-factor = 175 NAND2 Area = 3 PPoly  8 PM2 • (3 1.5 PM1)  (8  1.25 PM1) = 45 (PM1)2 = 180 F2 175 F2 M1 Half-Pitch (F) M2 pitch (PM2 1.25PM1) A-Factor (Alogic ,ASRAM) NWell Active Unit-Cell Area (Ulogic ,USRAM) Poly Contact M1 Contacted-poly pitch (PPoly 1.5PM1) M1 pitch (PM1) Transistor Density (Dlogic ,DSRAM) Contacted-poly pitch (PPoly 1.5PM1) Capacitance Density (Dcap,logic , Dcap,SRAM , Dcap,int) Power Density (Ddynamic ,Dstatic) MPU Power (P)

6. Transistor Density Model (U) Area of unit cells • Logic: • SRAM: (S) Area of MPU • Logic: • SRAM: (D) Density of MPU (#Tr. / Area) • Logic: • SRAM: M1 Half-Pitch (F) A-Factor (Alogic ,ASRAM) Unit area #gates per core Overhead #cores Unit-Cell Area (Ulogic ,USRAM) Transistor Density (Dlogic ,DSRAM) #bits per core Capacitance Density (Dcap,logic , Dcap,SRAM , Dcap,int) Power Density (Ddynamic ,Dstatic) MPU Power (P)

7. Power Density Model • Capacitance density • Dynamic power density • Active capacitancedensity • Dynamic power density • Static power density M1 Half-Pitch (F) A-Factor (Alogic ,ASRAM) • Cg: gate cap. per unit width from PIDS* • Cint: unit length interconnect capacitance from INT** • Wg: average width of a transistor (=5F) • Dl,max: maximum interconnect density (/cm2) from INT**, assuming every third track is occupied Unit-Cell Area (Ulogic ,USRAM) Transistor Density (Dlogic ,DSRAM) • : switching ratio, assumed as 15% in 2007 • : ratio of high performance (HP) transistors, assumed as 10% • : ratio of SRAM dynamic power to logic dynamic power Capacitance Density (Dcap,logic , Dcap,SRAM , Dcap,int) Capacitance Density (Dcap,logic , Dcap,SRAM , Dcap,int) •  of logic part uses HP transistors • Bitcell array (1/OSRAM) uses LSTP transistors •  of peripheral part uses HP transistors • (1- ) of peripheral part uses LSTP transistors Power Density (Ddynamic ,Dstatic) Power Density (Ddynamic ,Dstatic) MPU Power (P) *PIDS: Process Integration, Devices and Structure ** INT: Interconnect

8. New MPU Integration Scaling and Chip Size • Fast M1 half-pitch  Increases density • Number of cores: 2x / 2year (~2013), 2x / 3year (2014~) • Number of transistors per core: 2x / 2year (~2013), 2x / 3year (2014~) • Reduced A-factors • Logic A-factor: ~320  175 • SRAM A-factor: ~100  60  Reduced chip size • 310mm2  260mm2 • Logic area = #cores  #Logic Tr.  AF2 = ~100mm2 • SRAM area = #SRAM bits  9  6  AF2 = ~83mm2 • Integration overhead = 30% of total chip size = ~77mm2 Billion Transistors * Intel Core-i7: 263mm2 * AMD Opteron (Shanghai): 258mm2

9. Intrinsic Frequency Scaling • MPU frequency scaling follows transistor intrinsic delay (CV/I) scaling: • 13% per year • Dynamic power increases due to large active capacitance increases • Dynamic power reduction techniques must be developed • Switching activity ratio scaling factor: N = k N-1 k = 1 k = 0.95

10. Power-Constrained Frequency Scaling • Intrinsic frequency scaling + activity scaling  Still exceed 150W in 2015 • To meet market needs (130~150W for a platform), frequency improvement has to be limited: • 13% per year  8% per year, total power < 150W Power < 150W 8% frequency scaling

11. Conclusion • We have proposed a consistent, holistic modeling approach for MPU area/power/frequency roadmapping. From the model, • For future high performance MPU, aggressive dynamic power reduction techniques are strongly required • Frequency improvements need to be restricted: 8% per year • Ongoing work • We track tradeoff every year and make sure we don’t miss the frequency/#core/power curve tradeoff • We are considering doing a 2009 blind survey on frequency from key vendors

12. BACKUP

13. Outline • International Technology Roadmap for Semiconductors • Roadmap for Microprocessor • Recent Technology Roadmap Changes • Parameterized MPU Roadmap Models • Transistor Density Model • Capacitance Model • Power Model • Power-Constrained Frequency Model • Conclusion

14. History of ITRS 1991 Micro Tech 2000 Workshop Report National Technology Roadmap for Semiconductor (NTRS) - Semiconductor Industry Association (SIA) 1992 1994 1997 SIA Europe Japan Korea Taiwan USA International Technology Roadmap for Semiconductors (First Version - 1998 Update) Full Revision (Odd years) 1999 2001 2003 2005 2007 2009 2009 Update (Even years) 2000 Update 2002 Update 2004 Update 2006 Update 2008 Update

15. ITRS, System Driver, and MPU Emerging Research Materials Modeling & Simulation Test & Test Equipment Metrology Design Process Integration, Devices & Structure Process Integration, Devices & Structure Emerging Research Devices Environment, Safety & Health System Drivers System Drivers ITRS • Microprocessor (MPU) requires • Leading edge process and device • Highest frequency / integration / power • We develop a power-constrained MPU roadmap to tradeoff power and performance Interconnect Interconnect Yield Enhancement Assembly & Packaging Front End Processes Factory Integration Lithography RF and AMS

16. Capacitance Density Model • Capacitance density due to transistors • Capacitance of a transistor • Cg: gate cap. per unit width from PIDS* • Wg: average width of a transistor (=5F) • Capacitance density of transistors • Capacitance density due to interconnect • Dl,max: maximum interconnect density (/cm2) from INT**, assuming every third track is occupied • Dl,eff : effective interconnect density,1/3 (Dl,max), considering routing congestion and power/ground network • Cint: unit length interconnect capacitance from INT** M1 Half-Pitch (F) A-Factor (Alogic ,ASRAM) Unit-Cell Area (Ulogic ,USRAM) Transistor Density (Dlogic ,DSRAM) Capacitance Density (Dcap,logic , Dcap,SRAM , Dcap,int) Power Density (Ddynamic ,Dstatic) MPU Power (P) *PIDS: Process Integration, Devices and Structure ** INT: Interconnect

17. Power Model – Dynamic Power Density • Active capacitance density • Not all capacitances are working • : switching ratio, assumed as 15% in 2007 • Dynamic power density for logic area • : ratio of high performance (HP) transistors, assumed as 10% • Non-timing critical parts can have smaller activity (1/3) • Dynamic power density for SRAM area • SRAM can have different (maybe slower) frequency, different operation modes, e.g., disabled, different VDD, etc.  SRAM dynamic power estimation is hard! • : ratio of SRAM dynamic power to logic dynamic power M1 Half-Pitch (F) A-Factor (Alogic ,ASRAM) Unit-Cell Area (Ulogic ,USRAM) Transistor Density (Dlogic ,DSRAM) Capacitance Density (Dcap,logic , Dcap,SRAM , Dcap,int) Power Density (Ddynamic ,Dstatic) MPU Power (P)

18. Power Model – Static Power Density • Static power density for logic area • : ratio of high performance (HP) transistors, assumed as 10% • (1- ): ratio of low standby power (LSTP) transistors • Ioff,HP and Ioff,LSTP are from PIDS • Static power density for SRAM area • Bitcell array (1/OSRAM) uses LSTP transistors •  of peripheral part uses HP transistors • (1- ) of peripheral part uses LSTP transistors M1 Half-Pitch (F) A-Factor (Alogic ,ASRAM) Unit-Cell Area (Ulogic ,USRAM) Transistor Density (Dlogic ,DSRAM) Capacitance Density (Dcap,logic , Dcap,SRAM , Dcap,int) Power Density (Ddynamic ,Dstatic) MPU Power (P)