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Comparators

Comparators. Discussion D4.4. A 1-Bit Comparator. The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin = 0 and Lin = 0. The variable Lout is 1 if x < y or if x = y and Lin = 1.

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Comparators

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  1. Comparators Discussion D4.4

  2. A 1-Bit Comparator The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin = 0 and Lin = 0. The variable Lout is 1 if x < y or if x = y and Lin = 1.

  3. The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin = 0 and Lin = 0. The variable Lout is 1 if x < y or if x = y and Lin = 1.

  4. Gout = x * y' + x * Gin + y' * Gin Eout = x' * y' * Gin' * Lin' + x * y * Gin' * Lin' Lout = x' * y + x' * Lin + y * Lin

  5. A 4-Bit Comparator

  6. Comparators Recall that an XNOR gate can be used as an equality detector XNOR X if X = Y then Z <= '1'; else Z <= '0'; end if; Z Y Z = !(X $ Y) Z = X xnor Y Z = ~(X @ Y) X Y Z 0 0 1 0 1 0 1 0 0 1 1 1

  7. 4-Bit Equality Comparator A: in STD_LOGIC_VECTOR(3 downto 0); B: in STD_LOGIC_VECTOR(3 downto 0); A_EQ_B: out STD_LOGIC;

  8. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity eqdet4 is Port ( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); A_EQ_B : out std_logic); end eqdet4; architecture Behavioral of eqdet4 is signal C: std_logic_vector(3 downto 0); begin C <= A xnor B; A_EQ_B <= C0 and C1 and C2 and C3; end Behavioral;

  9. comp A_EQ_B A(n-1:0) A_GT_B A_LT_B B(n-1:0) A_UGT_B A_ULT_B Comparators A, B signed A, B unsigned Signed: 2's complement signed numbers

  10. -- Comparator for unsigned and signed numbers library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity comp is generic(width:positive); port ( A: in STD_LOGIC_VECTOR(width-1 downto 0); B: in STD_LOGIC_VECTOR(width-1 downto 0); A_EQ_B: out STD_LOGIC; A_GT_B: out STD_LOGIC; A_LT_B: out STD_LOGIC; A_ULT_B: out STD_LOGIC; A_UGT_B: out STD_LOGIC ); end comp; comp A_EQ_B A(n-1:0) A_GT_B A_LT_B B(n-1:0) A_UGT_B A_ULT_B

  11. architecture comp_arch of comp is begin CMP: process(A,B) variable AVS, BVS: signed(width-1 downto 0); begin for i in 0 to width-1 loop AVS(i) := A(i); BVS(i) := B(i); end loop; A_EQ_B <= '0'; A_GT_B <= '0'; A_LT_B <= '0'; A_ULT_B <= '0'; A_UGT_B <= '0'; if (A = B) then A_EQ_B <= '1'; end if; if (AVS > BVS) then A_GT_B <= '1'; end if; if (AVS < BVS) then A_LT_B <= '1'; end if; if (A > B) then A_UGT_B <= '1'; end if; if (A < B) then A_ULT_B <= '1'; end if; end process CMP; end comp_arch; comp A_EQ_B A(n-1:0) A_GT_B A_LT_B B(n-1:0) A_UGT_B A_ULT_B Note: All outputs must be assigned some value. The last signal assignment in a process is the value assigned

  12. 4-Bit Comparator

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