Tool for Customizing Fault Tolerance in a System

1. Tool for Customizing Fault Tolerance in a System Karan Maini and Sriharsha Yerramalla ECE 753 Project #10 May 1, 2014

2. Agenda • Introduction • Background and Related Work • Problem Statement Formulation • Implementation • Hardware Redundancy Techniques and FT Library • Synthesis Results – Area and Timing • Conclusion and Future Scope

3. Introduction • CAD Tools • Implementing electronic systems easier • Cut down on development time • Made verification process automated • CAD Tools for Fault Tolerance • Did not leverage advancements • Fault Tolerance was introduced manually • Being picked up in the recent past

4. Introduction • Need for Fault Tolerance • Real-time Systems • Operation Critical Systems • No guarantee of flawless execution • Applications • Banking • ATM Machines • Spacecraft • Satellites

5. Introduction • There has been several attempts made to develop an efficient tool without much manual intervention to introduce FT. • This could be at various levels of granularity. • Our attempt is to make FT at module level granularity.

6. The Challenge K IJ J F D A B C M E H G

7. The Plan K IJ J F D A B C M E H G

8. The Plan K IJ J F D A B C M H G

9. Solution K J A B B B B V V C

10. Agenda • Introduction • Background and Related Work • Problem Statement Formulation • Implementation • Hardware Redundancy Techniques and FT Library • Synthesis Results – Area and Timing • Conclusion and Future Scope

11. Background and Related Work • Hardware Redundancy • Insertion of F-T components into circuit • Done Manually (Old days) • Automatic Insertion Tools (At Present) • Process • Identify element(s) to be modified • Replication of selected element(s) • Selecting one set of output from different outputs coming from replicated element(s)

12. Background and Related Work • Hardware Redundancy (Contd.) • Initial Conditions – Input synthesizable design files • Pre-processing tasks – Identify type, number of elements present and their characteristics • Similar to simplified elaboration for synthesis • Specify the Hardware Redundancy technique to be followed

13. Background and Related Work • Information Redundancy • Selection of elements (Memory – IM, DM, Register Files) • Nearly entire module modification to deal with • Modification of data types and operators in order to process encoded information • Insertion of encoders, decoders and checkers in original design • Adding appropriate operators in F-T library • Declaration of target objects with the extra bits

14. Background and Related Work • Information Redundancy (Contd.) • Insert an encoder at a selected point • Extend the size of selected data to accommodate extra bits required by the redundant code used • Perform the functionality on the coded data • Insert a decoder/checker at a selected output point to get back the original data

15. Agenda • Introduction • Background and Related Work • Problem Statement Formulation • Implementation • Hardware Redundancy Techniques and FT Library • Synthesis Results – Area and Timing • Conclusion and Future Scope

16. Problem Statement Formulation Make a design Fault Tolerant by introducing components into the design using various Hardware Redundancy Techniques. Provide a Fault Tolerant Library to choose components from. Synthesize the original and new design to compare overhead introduced in terms of area and time.

17. Aim • Introduce Fault tolerance at Modular level • Target for Coarse granularity

18. Assumptions • User will input all the Synthesizable design files • At any given instant of time, only a single instance of a module may be fault prone. • User will only input files written in Verilog HDL

19. Agenda • Introduction • Background and Related Work • Problem Statement Formulation • Implementation • Hardware Redundancy Techniques and FT Library • Synthesis Results – Area and Timing • Conclusion and Future Scope

20. Taming the Bull • In which stage of design should this be tackled? RTL or netlist • In netlist – Finer control over granularity, but higher design complexity • In RTL – Difficult to have smaller granularity, butrelatively simple design • This is where our tool helps

21. Approach • Accept design files and top level module from user. • Identify different modules and their hierarchies present in the design. • Accept options from user. • Update the design with fault tolerance. • Verify the design.

22. Design Scheme of Fault Tolerant Insertion Tool

23. Front End - GUI Technology: Java Swing Look and Feel: Windows 8

24. Section 1 • Welcome Screen • Upload Design files • View/Update selected files • Enter top-level module • Fork() a child process to call back-end search engine

25. Section 2 • Hierarchical View • Returns from back-end • JTree Component used • Different levels – modules and instantiations • Singleton selection on leaf node - select an instance

26. Section 3 • Select Redundancy Type • Scan characteristics of Instantiated Module • Parameters passed • Bus-width of parameters • Introduction of Library Component into design • Success Message Dialog Box to inform user

27. Logical Components of Tool Search Engine GUI FT Insertion Library Front End Back End

28. Search Engine block • FT insertion block passes the Verilog design files to search engine block. • Searches for all modules in the design and populates them in an array. • Starts a recursive process to identify all the instances and their hierarchies. • Returns the hierarchical information to FT insertion.

29. Library • Following hardware redundancies are supported. • TMR • 5MR • Hybrid • Sift-out • Pair and Spare

30. TMR • Instance is replicated thrice and a Voter is added. Parameterized voter to support any bus width ALU1 Voter ALU2 ALU3

31. 5MR • Similar to TMR Voter…. ALU1 ALU2 Voter ALU3 ALU4 ALU5

32. Hybrid Redundancy • Implemented the design proposed by Daniel P. Siewiorek et al. • Made minor modifications to circuit to support scalability.

33. Implementation of Hybrid Redundancy P Voter P P S Comp block Status reg S

34. Sift-Out Modular Redundancy • Implemented the design proposed by Paulo T. De Sousa et al. • Made minor modifications

35. Implementation of Sift-out Redundancy P1 P2 P3 E C comparator and register

36. Pair and Spare P1 comparator Switch P2 P3 comparator P4

37. Library Options

38. Area and Delay Overhead

39. Micro-op Generator D Data Path Micro-op inst gen Offset_reg_num_gen FSM Reg_num_gen Offset_gen Inst_gen ALD ALD Inst_gen Offset_gen Priority Encoder

40. Area Overhead for Micro-op Generator • Area without FT – 7628.1

41. DUTs • PIIR filter • Micro-op Generator • 5 stage pipelined micro-processor

42. Future Work • Other types of hardware redundancies can be added to library modules without changing other parts of tools. • Information redundancy can also be added, but it will involve change in the tool and will need more information from user.

43. Conclusion • Tool that introduces fault tolerance in a Digital System is successfully developed. • The tool is tested on three different designs. • Overhead of various fault tolerance techniques is calculated and compared.

44. Tools Used • Java • Perl • Design Vision • Quartus